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| february 2001 zoran corporation ? 3112 scott blvd ? santa clara, ca 95054 ? (408) 919-4111 ? fax (408) 919-4122 data sheet ZR36067PQC-LV enhanced pci bus multimedia controller (low-voltage) features ? supersedes the zoran zr36057 and zr36067. ? glueless interface to pci bus (pci spec. 2.1 compliant). ? minimum interface to jpeg decoders (zr36060, zr36050+zr36016), mpeg1 and dvd decoders (zr36110, zr36700), video decoders and video encoders. ? bidirectional dma transfer of compressed data up to 11m bytes/sec. ? dma transfer of video and mask information. ? support for fast still image compression and decompression. ? smooth image down-scaler (up to 5-tap horizontal filter). ? on-chip pixel accurate masking. ? yuv-to-rgb converter with quantization noise reduction by error diffusion. ? video output: 15- and 16-bit rgb pixel formats, as well as 24-bit (packed and unpacked), and yuv 4:2:2. ? hardware support for non-contiguous jpeg code buffers. ? graceful recovery from extreme bus latencies both on video and code transfers. ? choice of emulated interlaced video display, or single field display, to eliminate motion artifacts. ? hardware support for simple, cost effective frame grabbing. ? i 2 c bus master port. ? plug & play support. ? 208-pin pqfp package. ? support for subsystem id and subsystem vendor id. applications ? high quality video and audio capture/playback and editing boards for pci systems. ? multimedia/graphics subsystems using a secondary pci bus. ? pci motherboards with multimedia capability. ? jpeg/mpeg1 solutions for powerpc and macintosh pci systems. video decoder audio control audio fifo audio codec zr36060 zr36067-lv video encoder graphics sub-system pci bus figure 1. block diagram of a typical motion jpeg system for pci
2 enhanced pci bus multimedia controller (low-voltage) enhanced pci bus multimedia controller (low-voltage) features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 the zr36067-lv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 jpeg system overview . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 motion video compression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 motion video decompression . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 still image compression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 still image decompression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 notations and conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 architectural overview . . . . . . . . . . . . . . . . . . . . . . . . 6 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . 8 digital video path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 digital video front end (vfe) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 video input processor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 pixel formatting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 video dma controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 pixel bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 display modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 frame grabbing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 overlay control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 host control/communication services . . . . . . . . . . . . . . . . .9 application-specific registers (asrs) . . . . . . . . . . . . . . . . . . . . . 9 guestbus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 postoffice handshaking protocol . . . . . . . . . . . . . . . . . . . . . . . . . 9 still transfer mechanism. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 i 2 c port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 interrupt manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 code dma controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 mpeg mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 jpeg modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 pci bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 digital video interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 sampling the incoming video . . . . . . . . . . . . . . . . . . . . . . . . . . 11 synchronization signal generation. . . . . . . . . . . . . . . . . . . . . . . 11 zr36067-lv connection to zr36060 video interface . . . . . . . 12 pixel transfer in still image compression mode . . . . . . . . . . . . 13 pixel transfer in still image decompression mode . . . . . . . . . . 13 guestbus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 flexible guestbus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 code-write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 doubleword to bytes mapping in code-write operations. . . . . . 14 postoffice operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 guestbus wait states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 postoffice handshaking protocol . . . . . . . . . . . . . . . . . . . .15 host writes to a guest device . . . . . . . . . . . . . . . . . . . . . . . . . 15 host reads from a guest device . . . . . . . . . . . . . . . . . . . . . . . 16 codec bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 compression mode code transactions . . . . . . . . . . . . . . . . . . . 16 decompression mode code transactions . . . . . . . . . . . . . . . . . 16 code bus stalling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 connecting zr36067-lv to zr36060 host and code intrfaces 17 i2c bus interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 general purpose i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . .17 interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 video input processor . . . . . . . . . . . . . . . . . . . . . . . 19 horizontal filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 horizontal/vertical downscaler . . . . . . . . . . . . . . . . . . . . . .19 color space converter . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 video output control . . . . . . . . . . . . . . . . . . . . . . . . 20 display modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 frame grabbing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 output pixel organization . . . . . . . . . . . . . . . . . . . . . . . . . .20 graphics overlay. . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 jpeg code transfer . . . . . . . . . . . . . . . . . . . . . . . . . 21 the code buffer table . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 fragment table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 jpeg compression modes . . . . . . . . . . . . . . . . . . . . . . . . .22 jpeg decompression modes . . . . . . . . . . . . . . . . . . . . . . .22 reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 hardware reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 software reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 jpeg p_reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 subsystem id and subsystem vendor id . . . . . . . 24 subsystem id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 subsystem vendor id . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 pci configuration space registers. . . . . . . . . . . . . 25 application-specific registers (asrs) . . . . . . . . . . 26 video front end horizontal configuration register . . . . . .26 video front end vertical configuration register. . . . . . . . .26 video front end, scaler and pixel format register . . . . . .27 video display top register . . . . . . . . . . . . . . . . . . . . . . .28 video display bottom register . . . . . . . . . . . . . . . . . . . . .28 video stride, status and frame grab register. . . . . . . . . .28 video display configuration register . . . . . . . . . . . . . . . . .28 masking map top register . . . . . . . . . . . . . . . . . . . . . . . .29 masking map bottom register . . . . . . . . . . . . . . . . . . . . .29 overlay control register . . . . . . . . . . . . . . . . . . . . . . . . . . .29 system, pci and general purpose pins control register .30 general purpose pins and guestbus control register (i) .30 mpeg code source address register . . . . . . . . . . . . . . . .30 mpeg code transfer control register. . . . . . . . . . . . . . . .31 mpeg code memory pointer register . . . . . . . . . . . . . . . .32 interrupt status register . . . . . . . . . . . . . . . . . . . . . . . . . . .32 interrupt control register . . . . . . . . . . . . . . . . . . . . . . . . . .32 i 2 c-bus register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 postoffice register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 jpeg mode and control . . . . . . . . . . . . . . . . . . . . . . . . . . .34 jpeg process control . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 vertical sync parameters . . . . . . . . . . . . . . . . . . . . . . . . . .35 horizontal sync parameters . . . . . . . . . . . . . . . . . . . . . . . .35 field horizontal active portion . . . . . . . . . . . . . . . . . . . . . .35 field vertical active portion . . . . . . . . . . . . . . . . . . . . . . . .35 field process parameters . . . . . . . . . . . . . . . . . . . . . . . . . .35 jpeg code base address . . . . . . . . . . . . . . . . . . . . . . . . .35 jpeg code fifo threshold . . . . . . . . . . . . . . . . . . . . . . . .35 jpeg codec guest id . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 guestbus control register (ii) . . . . . . . . . . . . . . . . . . . . . .36 still transfer register . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 3 enhanced pci bus multimedia controller (low-voltage) electrical characteristics . . . . . . . . . . . . . . . . . . . . . 37 absolute maximum ratings . . . . . . . . . . . . . . . . . . . 37 operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 ac timing specifications. . . . . . . . . . . . . . . . . . . . . .39 pci bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 video bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 guestbus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 codec bus interface timing. . . . . . . . . . . . . . . . . . . . . . . . 42 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 appendix a: zr36110 - zr36067-lv interface 46 zr36110 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 mapping the zr36110 on the zr36067-lvs guestbus . . . . 46 zr36110 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 on-line commands and status . . . . . . . . . . . . . . . . . . . . . . 46 bitstream transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 appendix b: md207/md208 - zr36067-lv interface 47 md207/208 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 mapping the md207/208 on the zr36067-lv s guestbus . . 47 sync polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 vertical interpolation with the md208 . . . . . . . . . . . . . . . . . . 47 appendix c: fitting the input size to the required display window 48 calculating the horizontal parameters:. . . . . . . . . . . . . . . . . . . . . . . . 49 calculating the vertical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . 49 4 enhanced pci bus multimedia controller (low-voltage) 1.0 introduction 1.1 the zr36067-lv the zr36067-lv is a pci adapter intended for multimedia appli- cations on pci systems. it supports high rate code (compressed data stream) transfer between the system memory and jpeg or mpeg processors. simultaneously to the code transfer, the zr36067-lv captures digital video, such as decompressed mjpeg (motion jpeg), mpeg, or the output of a video decoder, and creates a scaled video window in the graphics display memory. the zr36067-lv provides the host software with full control over a large number of non-pci multimedia devices: ? motion jpeg codecs - zr36050+ zr36016, zr36060 ? audio codecs ? mpeg and dvd decoders - zr36110, zr36700 ? i2c devices, such as video decoders, video encoders, etc. the zr36067-lv interfaces directly to the pci bus. as a bus master, it transfers data (e.g, jpeg compressed data) to or from the system memory, and writes digital video pixels to the graphics display memory. as a bus target, the zr36067-lv reflects the host accesses onto a micro-controller-type 8-bit guest bus. the zr36067-lv has a special still transfer port by means of which the host software writes (or reads) digitized video, as rgb pixels, from the system memory to (or from) the video bus. this path enables fast transfer of still images to be compressed (or decompressed) by the jpeg chip set. the zr36067-lv supersedes both the zr36067 and zr36057 pci bus multimedia controllers and is recommended for all new designs. like the zr36067, the zr36067-lv has the same package, pinout and functions and the zr36057, with the follow- ing exceptions: ? the zr36067-lv supports programmable pci subsystem id and subsystem vendor id. these id registers get their values by sampling the state of existing pins of the zr36067-lv (video bus, guest bus and gpio pins) at pci reset time. thus, the values can be programmed by means of pull-up or pull-down resistors on these pins. note that the subsystem id and subsystem vendor id registers of the zr36057 are hard wired to 0. ? two functional bugs of the zr36057, documented in its data sheet, have been corrected in the zr36067-lv and work- arounds are no longer required. the zr36067-lv is functionally identical to the zr36067. 1.2 jpeg system overview figure 1 depicts an example of an mjpeg add-on board, using the zr36067-lv and zr36060. the zr36067-lv supports 4 basic jpeg modes of operation: ? motion video compression. ? motion video decompression. ? still image compression. ? still image decompression. 1.2.1 motion video compression the video decoder directs the video in yuv 4:2:2 format, and the video synchronization signals, to the video input port of the zr36060. the video is also transferred to the video encoder for display on a tv monitor and simultaneously to the video front end of the zr36067-lv. the zr36067-lv can optionally down- scale the video, convert it to rgb, and transfer the pixels using dma to the display memory of the host pc. in parallel, the zr36060 performs the jpeg compression. the zr36050 drives the jpeg code stream to the codec front end of the zr36067- lv, which transfers the compressed video fields using dma to a system memory buffer allocated by the host. 1.2.2 motion video decompression in motion video decompression, the zr36067-lv transfers the code stream from system memory via the zr36067-lv codec front end to the zr36060, using dma. the zr36060 decom- presses the jpeg code and transfers the video to the video encoder to be displayed on a tv monitor. the zr36060 video output is driven simultaneously to the video front end of the zr36067-lv to be processed, as in the compression mode, and transferred using dma to the pc display memory. 1.2.3 still image compression in still image compression mode an image bitmap is written by the host, pixel by pixel, through the pci bus to the zr36067-lv. the zr36067-lv transfers the pixels through its video bus port to the video input port of the zr36060. the zr36067-lv gener- ates and drives the required video synchronization signals for the zr36060 in this mode. after the first strip of 8 video lines is filled, the zr36060 starts performing the raster-to-block opera- tion and compressing the data, and drives the code stream to the zr36067-lv. the code stream is transferred using dma to the host memory as in motion video compression. 1.2.4 still image decompression in still image decompression mode, the zr36067-lv fetches the code stream from system memory using dma, as in motion video decompression. the zr36060 reads the compressed data from the zr36067-lv, decodes it and send the decom- pressed video to the video port of the zr36067-lv. from there the host software reads it out to system memory, pixel by pixel. note that still image decompression can also be accomplished by configuring the zr36067-lv in motion video decompression 5 enhanced pci bus multimedia controller (low-voltage) mode, and transferring the decompressed video to a contiguous buffer in system memory instead of the display memory. since this has a speed advantage over still image decompression mode, it is the preferred method for most applications. 1.2.5 notations and conventions external signals: capital letters (e.g., idsel) active-low mark [1] : overbar (e.g., devsel ) internal function units: capital (non-bold) letters (e.g., vfe) buses: xxmsb_index..lsb_index (e.g., ad31..0) register fields: xxmsb_index:lsb_index (e.g., mode27:16) register types: r - read only rc - read-clear. writing 1 clears the register bit. rs - read-set. writing 1 sets the register bit to 1. rw - read-write (contents of write can be read back) w - write only (contents of read are meaningless) numbers: unmarked numbers are decimal (e.g., 365, 23.19). hexadecimal numbers are marked with a 0x prefix (e.g., 0xb000, 0x3). binary numbers are marked with a b suffix (e.g., 010b, 0000110100011b). 1. in this document, an overbar is used to denote active low signals. in other documents referenced herein, such as the pci spec ifications, the # suffix notation is often used instead. the two forms of notation are interchangeable. thus, for example, devsel is equivalent to devsel#. 6 enhanced pci bus multimedia controller (low-voltage) 2.0 architectural overview the zr36067-lv architecture contains two main data paths, the video path and the code path. the incoming video is processed along the video path and transferred to the graphics display memory using pci dma bursts. the zr36067-lv video front end samples the video bus within a programmable active field window, defined with respect to the video synchronization signals. an optional vertical and horizon- tal smooth scale down can be applied, in order to support variable image sizes and variable pci video data rate. the scaled video stream can be converted to various rgb formats. the converted pixels are packed and stored in a 256-byte video fifo, organized as 64 32-bit doublewords. the stored video pixels are read from the video fifo and transferred to the graphics display memory according to a display masking map controlled by and stored inside the zr36067-lv. the code path is bidirectional. the data flow direction depends on the mode of operation. the code stream (mpeg or jpeg) is transferred between system memory and the internal code fifo of the zr36067-lv using pci dma bursts. the zr36067- lv controls the transfer and addressing in both directions. the code fifo size is 640 bytes, organized as 160 doublewords. in jpeg compression modes the zr36067-lv codec front end fills the code fifo. from the code fifo the code is trans- ferred to the system memory, field by field. in jpeg decompression modes the code stream flows in the opposite direction, from the system memory to the zr36067-lv code fifo. the codec front end reads out the code fifo byte by byte onto the code bus. in mpeg playback mode, the code stream is transferred to the zr36067-lv code fifo from the system memory. the code bytes are read from the code fifo out to the guest bus. the zr36067-lv video and the code paths operate simulta- neously while the zr36067-lv arbitrates the pci bus requests for each process. besides managing the video and code paths, the zr36067-lv bridges the host cpu to peripheral devices (known as guests). using a dedicated handshaking mechanism (the postoffice mechanism), host accesses to an internal zr36067-lv register are reflected to the guest bus in order to enable indirect host read and write operations to the guests. the zr36067-lv contains a dedicated still transfer port which enables data flow between the pci interface and the video front end. using a specific handshake protocol, the host software may transfer digitized video (rgb pixels) from the system memory to the video bus, and vice versa. this path enables very fast transfer of still video images to be compressed or decom- pressed by the jpeg codec. video front end (vfe) figure 2. zr36067-lv block diagram vclk, vclkx2 vsync, hsync fi rtbsy start, pxen y[7:0] uv[7:0] b[7:0] video input processor video fifo video dma controller guest bus master gcs[7:0] gad[2:0] grd , gwr grdy gws gdat[7:0] scl sda i 2 c port application specific registers gpio[7:0] pci interface codec front end (cfe) cend ccs cbusy code[7:0] code fifo code dma controller interrupt manager girq[1:0] 7 enhanced pci bus multimedia controller (low-voltage) 3.0 pin descriptions symbol type [1] direction description pci interface (48 pins) ad[31:0] 3-state i/o multiplexed address and data bus pins. c/be [3:0] 3-state i/o bus commands or byte enables. par 3-state i/o even parity bit for ad31..0 and c/be [3:0]. frame 3-state* i/o pci cycle frame. trdy 3-state* i/o pci target ready indicator. irdy 3-state* i/o pci initiator ready. stop 3-state* i/o indicates a target request to stop the current data transfer. devsel 3-state* i/o pci device select, indicates that the target has decoded its address. idsel i i pci initialization device select. used as a chip-select to the zr36067-lvs configuration space. req 3-state o pci bus request. gnt 3-state i pci bus grant. pciclk i i pci clock. pcirst i i pci reset. when active, all zr36067-lv output pins are tri-stated. a low to high transition puts the zr36067-lv into its power-on reset state. minimum active low duration is 3 pci clocks. inta open drain o pci interrupt request a. a low level on this signal requests an interrupt from the host. digital video bus interface (32 pins) y[7:0]/r[7:0] 3-state i/o luminance/red video lines. also used to program the low byte of subsystem vendor id. uv[7:0]/g[7:0] 3-state i/o chrominance/green video lines. also used to program the low byte of subsystem id. b[7:0] 3-state i/o blue video lines. vclkx2 i i double frequency video bus clock. vclk i i digital video bus clock. used as a qualifier to vclkx2. must be synchronized to vclkx2. hsync 3-state i/o digital video bus horizontal sync. vsync 3-state i/o digital video bus vertical sync. fi i i digital video bus field indicator (top/bottom). pxen o o active low pixel enable output to the zr36016. rtbsy i i active low strip memory overflow/underflow signal from the zr36016. start o o active high start process output to the zr36016. guestbus interface (25 pins) gcs [7:0] o o active low chip-select output to guest bus devices. gadr[2:0] o o address outputs to guest bus devices. gdat[7:0] 3-state i/o guest data bus. also used to program the high byte of subsystem vendor id. grd o o active low read output to guest bus devices. gwr o o active low write output to guest bus devices. grdy i i active high guest ready input, used only in mpeg code-dma mode as a data request. gws i i guest wait-state indication. assertion of this active-low input allows the guest device to extend the guestbus write (or read) cycle until it is capable of latching-in (or providing) the data. girq[1:0] i i positive-edge-sensitive interrupt request inputs from one or two of the guest bus slave devices. codecbus interface (11 pins) code[7:0] 3-state i/o code bus connected to the zr36050. cend i i active low end of field process indication from the zr36050. ccs i i active low code bus active cycle signal from the zr36050. cbusy o o active low code fifo busy indication to the zr36050. i2c bus interface (2 pins) sda od i/o i 2 c bus data 8 enhanced pci bus multimedia controller (low-voltage) 4.0 functional overview the zr36067-lv multimedia controller performs the following functions: ? interfacing to a yuv 4:2:2 digital video bus (e.g., phillips saa7110 or saa7111). ? video dma channel for burst transfers of video pixels. ? independent horizontal and vertical downscaling of the input image, with optional horizontal filtering. ? optional sync mastering with configurable hsync and vsync pulse widths and polarity. ? conversion of the yuv 4:2:2 digital video input into one of the following pixel formats: yuv 4:2:2, rgb 5,6,5, rgb 5,5,5 or rgb 8,8,8 (packed or unpacked). ? overlay support: any number of video pixels can be masked off, letting the corresponding graphics pixels appear instead of them. ? frame grabbing. ? two display modes: emulation of the interlaced input video, or a single field display. ? bidirectional code dma transfer with support for fragmented code buffers. ? control of the zr36060 motion jpeg codec or zr36050/ zr36016 motion jpeg chip set. the zr36067-lv supports digital video in ccir 601 or square pixel formats, following either the ntsc or pal video standard. other non-standard input schemes are supported as well. the functional description below follows the block diagram. 4.1 digital video path 4.1.1 digital video front end (vfe) the vfe samples the incoming yuv 4:2:2 video data and sync signals with a flexible sampling scheme, that makes it compati- ble with a wide variety of digital video sources. the digital input video can be cropped. the input resolutions supported by the vfe range from 32x32 to 1023x1023, in increments of one pixel. 4.1.2 video input processor the chroma components of the video data are upsampled to yuv 4:4:4 format. all components are horizontally filtered. five filtering schemes are implemented, with different parameters for chrominance and luminance samples. horizontal and vertical downscaling is available if required. the vertical downscaling can be optimized for live video or full screen motion jpeg play- back, in which each field is independent, or for the output of an mpeg-1 decoder, which duplicates fields to produce its inter- laced video output. 4.1.3 pixel formatting the filtered and scaled video is converted to the desired color space and packed according to the selected pixel format. yuv 4:2:2, 24-bit rgb (packed or unpacked) and 15- and 16-bit rgb are supported. an error diffusion algorithm can be applied to the rgb 5,5,5 and 5,6,5, in order to eliminate quantization artifacts on the output image. scl od i/o i 2 c bus clock (qualifies for a single master operation only). general purpose programmable inputs/outputs (8 pins) gpio[7:0] 3-state i/o general purpose input/output pins. after hardware or software reset all 8 pins are configured as inputs. their logical levels are reflected as register bits. any of the pins can be configured as output. in this state its logical level is driven by a register bit. these pins may be used to monitor or control various board-level functions. also used to program the high byte of subsystem id. test pins (2 pin) enid test i used for idd test. in normal operation must be connected to gnd. test test i test pin used in test mode only. in normal operation must be connected to gnd. power (80 pins) gnd ground ground (50 pins). vddio power i/o power supply (5v) (23 pins). vddc power core power supply (3.3v) (7 pins) 1. i - standard input-only ? o - standard active driver ? 3-state - bidirectional i/o pin ? 3-state* - a special type of 3-state , as defined in the pci spec. may be driven by only one pci agent at any time ? od - open drain, may be shared by multiple drivers, as a wired-or. 3.0 pin descriptions (continued) symbol type [1] direction description 9 enhanced pci bus multimedia controller (low-voltage) 4.2 video dma controller 4.2.1 pixel bursts the packed pixels are transferred directly to the display memory (or to the system memory), using pci dma bursts. both little and gib endian formats are supported where applicable (refer to the pci multimedia design guide, revision 1.0). 4.2.2 display modes the display mode can be configured to either emulated inter- laced video (both input fields are displayed simultaneously on the non-interlaced monitor) or single field display. the latter is appropriate for motion artifact elimination when displaying live or decompressed motion jpeg video. 4.2.3 frame grabbing the zr36067-lv can grab video frames (scaled or non scaled), or fields, in any of the pixel formats listed above, directly into system memory, eliminating the need for memory on the add-in board. 4.2.4 overlay control graphics overlay is supported, in that display memory areas that are owned by graphics applications, may not be loaded with video pixels, allowing true windowing and overlay. the software driver prepares a masking map of the video rectangle, and the zr36067-lv uses this map for masking decision, when transfer- ring the pixels to the display memory. 4.3 host control/communication services 4.3.1 application-specific registers (asrs) the name application-specific distinguishes these registers from the pci configuration space registers. these memory mapped registers provide the host software with full control over the operation of the zr36067-lv. the zr36067-lv claims a contiguous space of 4 kbytes in system memory. 4.3.2 guestbus host software control over non-pci devices, such as a motion jpeg codec, an mpeg decoder, a video encoder, etc., is done through the zr36067-lvs guestbus. host accesses to these guest devices, mapped as application specific registers inside the zr36067-lv, are output as guestbus cycles. such accesses can either use the postoffice handshaking protocol, or the code dma controller. the first method is adequate for com- mands, configuration data, etc., while the second method provides a faster channel, and is intended for continuous transfer of data such as a compressed bitstream. 4.3.3 postoffice handshaking protocol the zr36067-lv postoffice handshaking protocol, implement- ed over the guestbus, allows host accesses to relatively slow guest devices, with no degradation of the pci bus performance. 4.3.4 still transfer mechanism the zr36067-lv supports a dedicated still transfer port, by means of which the host writes (reads) image pixels in jpeg still image compression (decompression) mode. the still transfer port is mapped inside the asr area, and a special controller interconnects this port to the zr36067-lvs extended video bus (24 bits rgb). the still transfer handshake protocol enables high rate pixels transfer between the system memory and the jpeg processor via the zr36067-lv. 4.3.5 i 2 c port a software-driven i 2 c port allows controlling of i 2 c devices. 4.3.6 interrupt manager interrupt requests associated with several internal and external conditions are sent to the host via the pci bus (using inta ). selection of interrupt originators is programmable. 4.4 code dma controller the zr36067-lv includes a dma channel for transferring data between the system memory and a selected device on the code bus or guestbus. two configurations are supported: ? mpeg mode. the data flow is unidirectional, from the sys- tem memory, to the zr36067-lvs guestbus. ? jpeg mode. the data flow is bidirectional, and the direction is determined by the selected sub-mode. in jpeg compres- sion, the data flows from the codec bus to the system memory. in jpeg decompression, the data flows from the system memory to the codec bus. 4.4.1 mpeg mode in mpeg mode, the data flows from the system memory to the zr36067-lvs guestbus. typically, this would be a compressed bitstream, to be decompressed by a device such as an mpeg decoder attached to the guestbus. other examples are sampled audio (wav data), midi token stream, etc. temporary latencies on the pci bus or the guestbus are handled without loss of data. the guestbus master simultaneously serves the postoffice accesses and the code dma transfers: dma transfers are viewed as the main task of the guestbus master, while any number of postoffice requests may occasionally interrupt the dma traffic. the dma controller supports both auto-initialized (cyclic) block transfers, or single block transfers. the size of the destination block in main memory can be selected out of several possible sizes, ranging from 8 kbytes up to 256 kbytes. the destination 10 enhanced pci bus multimedia controller (low-voltage) block may also be virtually split into several sub-blocks, allowing the zr36067-lv to interrupt the host when a sub-block has been transferred. this feature provides the software with a means of optimizing the refill accesses according to the application requirements and the disk performance. 4.4.2 jpeg modes in the jpeg modes, the data flows between the system memory and the zr36067-lvs codec bus. in jpeg compression, from the codec bus to the system memory; in jpeg decompression, from the system memory to the codec bus. the jpeg code data inside the system memory is structured within code buffers. each code buffer may contain a com- pressed field or a frame (2 fields), in accordance with a user configurable register bit. the zr36067-lv supports four code buffers, defined dynamical- ly in a dedicated table (the code buffer table) in the system memory. the actual memory of each code buffer may be frag- mented. the content of each entry in the code buffer table is a pointer to a secondary fragment table. the fragment table contains the pointers to the allocated memory chunks (fragments). in jpeg compression mode, the host software builds and updates the code buffer table and the fragment tables according the memory allocated by the operating system. on every jpeg field/frame process, the zr36067-lv code dma controller reads the fragment table pointer of the current buffer from the code buffer table, and then fills up the buffer fragments one by one. in jpeg decompression mode, the host software builds the code buffer table and fragment tables, and fills the fragments with the compressed field or frame. on every jpeg process, the zr36067-lv code dma controller retrieves the code fragments one by one, and directs them to the codec bus. 5.0 interfaces 5.1 pci bus interface in general, the zr36067-lv is compatible with the pci 2.1 spec- ifications. as a bus master, it may initiate two types of data transfer over the pci bus: ? memory write (pci command 0111b), from the zr36067- lvs video fifo buffer to the display memory (or main memory), and from zr36067-lvs code fifo buffer to the system memory. ? memory read line (pci command 1110b), from system memory to the zr36067-lvs mask buffer [1] and from sys- tem memory to the zr36067-lvs code fifo buffer. as a bus target, the zr36067-lv responds to the following types of transfer: all other pci commands are ignored. memory read line and memory read multiple are handled exactly like memory read. normally, as a slave, the zr36067-lv is intended to be accessed with single data phase cycles. however, multiple phase bursts are supported. when the zr36067-lv is accessed in a burst it increments its internal (offset) address such that each data phase is routed to/from the next address location (in doublewords). the zr36067-lv supports byte enables, such that an access to explicit bytes is possible. the error reporting signals, serr and perr , are not included in the zr36067-lv: as a multimedia device it is only required to report parity errors through the pci status register. the zr36067-lv uses the inta pci interrupt request line. 5.2 digital video interface the zr36067-lv interfaces to a wide spectrum of digital video devices. the video interface is bidirectional and two video pixel flows are supported: ? the incoming video is sampled and directed via the zr36067-lvs video input processor to the graphics display memory or system memory. ? the video pixels are transferred to or from the system mem- ory using a dedicated mechanism (the still transfer mechanism). the zr36067-lv supports two sync signal source configuration options: ? external sync - the sync signals are driven by the external video source. ? internal sync - the sync signals are generated internally and mastered by the zr36067-lv. in jpeg motion video compression and decompression modes as well as in mpeg mode, the video interface transfers the incoming video to the zr36067-lvs video input processor. the 1. not shown in the block diagram. memory read (0110b) memory read line (1110b) memory read multiple (1100b) memory write (0111b) configuration read (1010b) configuration write (1011b) 11 enhanced pci bus multimedia controller (low-voltage) sampling of the video stream is performed according to the video clocks and sync signals. in jpeg motion video compression mode and in mpeg mode, the synchronization source should be external. in jpeg motion video decompression mode, the syn- chronization source can be either external or internal. in jpeg still image compression and decompression modes, the zr36067-lv uses a dedicated mechanism (the still transfer mechanism) as a means for the host software to transfer pixels to or from the compression module. the video interface masters the extended 24-bit video bus and the synchronization signals in order to drive the pixels to the zr36016 or get them from it, as appropriate. the following four subsections detail the four basic functions of the video interface: ? sampling the incoming video. ? generating the synchronization signals. ? pixel transfer in still image compression. ? pixel transfer in still image decompression. 5.2.1 sampling the incoming video the zr36067-lvs video front end (vfe) interfaces to a standard yuv 4:2:2 video bus. it samples the y7..0, uv7..0, hsync and vsync with every other positive edge of vclkx2. the valid positive edge (out of every two consecutive ones), which is the one used for sampling, is qualified by vclk. the qualifying polarity of vclk is configured by the host. this scheme makes the zr36067-lv compatible with a wide range of digital video sources and immune to board-level parasitic delays. vclkx2 (positive edges) is used internally in the video processing pipeline. the vfe generates a field indication signal targeted to some internal video processing units. there are two alternative ways of generating the field indication. with devices that output a field indication, the vfe uses the fi input as an indicator of the current field identity. the interpretation of the logical level of fi (top or bottom field) is configured by the host. with devices that do not provide such an indication, the vfe infers the field identity from the relationship of hsync to vsync. the vfe can capture square pixel and ccir-601 formats, or user defined formats, within the limitation of its parameters. the maximum theoretical total input resolution is 1023 pixels/line x 1023 lines per frame. cropping of the input image is possible by proper configuration of the vfe parameters. table 1 lists the video front end parameters. the host software needs to configure these parameters according to the timing parameters of the video source (e.g., saa7110, saa7111, zr36060, etc.) and the required cropping. note that these parameters relate to the input video, and not to the destination 5.2.2 synchronization signal generation the zr36067-lv supports internal generation of the video syn- chronization signals. in this mode (when syncmstr =1) the zr36067-lv generates and drives vsync and hsync signals. using software programmable parameters, the zr36067-lv can generate various video synchronization signal formats. table 3 lists the sync signal parameters. the host software con- figures those parameters according the mode of operation and the video peripheral devices used. note that he polarity of the sync signals is determined by the vspol and hspol parameters (table 2). table 1: video front-end parameters parameter description vstart number of lines (hsyncs) from the active edge (pos- itive or negative, according to vspol) of vsync to the first line to be sampled. hstart number of pixel clocks in a line from the active edge of hsync until the first pixel to be sampled. vend number of lines (hsyncs) from the active edge (pos- itive or negative, according to vspol) of vsync to the last line to be sampled. hend number of pixel clocks in a line from the active edge of hsync until the last pixel to be sampled. extfi this one bit parameter indicates whether the video source provides a field indication signal. hspol the hsync polarity. hstart and hend are counted from the active edge of hsync. 1 means that hstart, hend will be counted from the negative edge of hsync. also determines signal polarity when syncmstr=1. vspol the vsync polarity. vstart and vend are counted from the active edge of vsync. 1 means that vstart, vend will be counted from the negative edge of vsync. also determines signal polarity when syncmstr=1. topfield top field interpretation. if field indication is derived from the fi input signal (see extfi), topfield indicates the interpretation of the fi signal: topfield=1 - fi high indicates the top field. topfield=0 - fi low indicates the top field. if field indication is derived internally from hsync and vsync, topfield indicates the interpretation of the level of hsync as sampled by the active edge of vsync: topfield=1 - hsync high indicates the top field. topfield=0 - hsync low indicates the top field. vclkpol polarity of vclk as a data qualifier. if vclkpol=1 the video input is sampled with those positive edges of vclkx2 that correspond to vclk=1. if vclkpol=0, the video input is sampled by those positive edges of vclkx2 that correspond to vclk=0. 12 enhanced pci bus multimedia controller (low-voltage) table 2: synchronization signal parameters the zr36067-lv video interface drives out the video synchro- nization signals synchronized with the negative edge of vclkx2 (every other edge). the vclk input is used as a phase qualifier. the timing of the rising and the falling edges of vsync with respect to the hsync signal are: ? odd fields - the edges of vsync occur in the middle of the non-active portion of hsync. ? even fields - the edges of vsync occur in the middle of the active portion of hsync. 5.2.3 zr36067-lv connection to zr36060 video interface figure 3 shows the recommended connections between the zr36067-lv and the zr36060 video interface. for recom- mended connections between the zr36067-lv and the zr36016 video interface, refer to the zr36057 data sheet. in motion video compression, the yuv video and synchroniza- tion signals are driven by the external video source (for example, a saa7110) to the inputs of the zr36067-lv and zr36060. in motion video decompression, the synchronization signals are driven by the zr36067-lv (in sync master mode) or by an external sync generator, associated with the video source. the decompressed digital video is transferred from the zr36060 video bus to the zr36067-lv video interface. the video bus of the external video source, and if necessary its sync signals, must be forced to float, typically using software control. in still image compression, the video bus as well as the sync signals are driven by the zr36067-lv. therefore, the video bus of the external video source (such as the video decoder of figure 1), and if necessary its sync signals, must be forced to float. in still image decompression mode, the sync signals are driven by the zr36067-lv. decompressed video is transferred from the zr36060 to the zr36067-lvs video interface. in this mode of operation, the video bus and sync signals of an external video source (such as the video decoder of figure 1) must be forced to float. table 3 defines the zr36060 and zr36067-lv parameters which define the portion of the field to be processed (the active portion). 5.2.3.1 start signal control the start signal is used with the zr36016 only, to start the compression/decompression process at the correct time for the desired field type. 5.2.3.2 pxen signal control the zr36067-lv drives the pvalid input of the zr36060. while pvalid is deactivated, the zr36060 does not sample the video bus and the video sync inputs. to keep the zr36067-lv and the zr36060 synchronized, deac- tivation of pxen by the zr36067-lv also holds the horizontal counting and processing inside the zr36067-lv. in motion video compression mode, pxen is activated continuously. in motion video decompression mode, pxen is asserted by then zr36067-lv after latching the rising edge of rtbsy , indi- cating that the first strip is ready in the zr36060 strip memory. parameter meaning frmtot total number of lines per frame (e.g., in ntsc: 525) linetot total number of pixel clocks per line (e.g., in ccir ntsc: 858) vsyncsize the length of the vsync signal, measured in lines. hsync start the point in the scan line at which the hsync signal should be asserted. figure 3. recommended connection of zr36067-lv to zr36060 video interface vclk vclkx2 vsync hsync yuv[15:0] pvalid rtbsy poe vclk vclkx2 vsync hsync yuv[15:0]/rgb[23:0] pxen rtbsy from external video source zr36060 zr36067-lv table 3: parameters defining the active portion of a field zr36067-lv parameter zr36060 parameter meaning nax hstart the number of pixels to be skipped, counted from the active edge of hsync. pax hend-hstart the number of active pixels in a line. nay vstart the number of lines to be skipped counted from the active edge of vsync. pay vend-vstart the number of active lines in a field. odd_even fidet with the frame signal 13 enhanced pci bus multimedia controller (low-voltage) in still image compression mode, the image is transferred to the zr36067-lv by the host software pixel by pixel. pxen is activat- ed only when a pixel is ready to be sent out from the zr36067- lv video interface to the zr36060 video input. in still image decompression mode, the image is read from the zr36067-lv by the host software pixel by pixel. pxen is activat- ed to get the next pixel from the zr36060 only after the previous pixel has been read by the host. pxen can be de-asserted dynamically (in the middle of a process) in response to several different conditions. the dynamic de-assertion is enabled independently by three config- uration bits - vfifo_fb, cfifo_fb, rtbsy_fb. the host software is allowed to set those bits only while the zr36067-lv is the sync master. when vfifo_fb is set, if the video fifo is close to overflow status, pxen is de-asserted to hold the zr36060 video output until the video fifo is emptied. when cfifo_fb is set, if the code fifo underflows, and cbusy is asserted, pxen is de- asserted to hold the zr36060 video output until the code fifo is filled. when rtbsy_fb is set, if rtbsy is asserted by the zr36060 during the active portion of the field, pxen is de- asserted until rtbsy is de-asserted. 5.2.3.3 rtbsy signal control the zr36067-lvs rtbsy input is connected to the zr36060s rtbsy output. the zr36067-lv uses rtbsy to detect overflow and underflow conditions in the zr36060 strip memory. in motion video compression mode, if rtbsy is asserted when the first active pixel of a line is sampled, a condition that indi- cates a strip buffer overflow, the zr36067-lv abandons the compression process for the field and waits for the beginning of the following field. in motion video decompression mode, de-assertion of rtbsy is used to decide when to initiate the decompression process. in all modes, when rtbsy_fb is set, rtbsy is checked by the zr36067-lv at the following times: ? before the trailing edge of vsync, which triggers the start of a new field process in the zr36060, ? during the active portion of the field. the zr36067-lv de-asserts pxen if rtbsy is asserted at those times. pxen is asserted again after rtbsy is de- asserted. 5.2.4 pixel transfer in still image compression mode the image is transferred by the host software to the zr36067- lvs extended 24-bit video bus. the host writes the pixels one by one to a dedicated register (the still transfer register) in the zr36067-lv. each pixel is synchronized with the video clock and transferred to the video interface port. two modes of host access are supported: ? the host verifies, by polling, the availability of the still trans- fer register before each pixel write access. typically, this mode would be used after writing the first pixel of each line, before writing the remainder of the line. ? the host configures the waitstate parameter and writes the pixels continuously to the still transfer register. the zr36067-lv de-asserts the pci trdy signal every host ac- cess with the timing specified by the waitstate parameter. typically, this mode would be used to transfer the pixels of a line after the first. the still transfer write protocol and the associated internal mechanism of the zr36067-lv are described below: ? the host writes a pixel using a single data phase memory write cycle. the pixel is latched in the still transfer register using the pci clock. ? the still_bsy bit is set. ? the incoming pixel is synchronized with the video interface clock. the pxen output signal is asserted and the pixel is driven out on the correct video clock phase. ? feedback from the video interface resets the still_bsy bit, indicating that the video port is empty and the following host write is permitted. 5.2.5 pixel transfer in still image decompression mode the image is transferred from the zr36067-lvs extended 24- bit video bus to system memory. the host software reads the pixels one by one from the still transfer register. after each pixel is fetched from the video port, it is synchronized with the pci clock, ready to be read by the software. before each read access, the host software should check the still_bsy bit to verify availability of data in the register. the register contents are valid only if the still_bsy bit is 0. note that by configuring the waitstate parameter, it is possible to ensure that the still transfer register will be valid every read access, making it unnecessary to check the still_bsy bit. the protocol for a still image decompression read operation, and the zr36067-lvs behavior, are as follows: ? the zr36067-lv checks the still_bsy bit. if it is 1, meaning that the previous valid pixel was read by the host, the zr36067-lv fetches a new pixel from the zr36016. ? pxen is asserted, causing a new pixel to be driven onto the video bus. ? the new pixel is synchronized with the pci clock and latched in the still transfer register. ? still_bsy is reset to 0, to indicate that a new valid pixel is available. ? the host software reads the pixel by means of a memory read access to the still transfer register, and still_bsy is set to 1. 14 enhanced pci bus multimedia controller (low-voltage) 5.3 guestbus interface the zr36067-lv masters a generic mcu-style bus intended to concurrently host up to eight slave devices (referred to as guests). the bus consists of 8 data lines (gdat[7:0]), 3 address lines (gadr[2:0]), 8 active-low chip-select lines (gcs [7:0]), read and write signals (grd , gwr ), and a wait- state insertion line (gws ). the bus also includes two interrupt- request inputs (girq[1:0]) and one status/acknowledge input (grdy). three types of data transfers are possible on the guest bus. one is a code-write cycle, initiated by the code dma con- troller of the zr36067-lv, targeted to one of the guests, configured a-priori for such write cycles [2] . the second is a go command to the zr36050 (configured a priori as one of the guests) in jpeg mode; the same type of bus cycle can be used to toggle the start pin of the zr36060. the third is a postof- fice cycle, initiated by the host software, targeted to any one of the eight guests; in particular, postoffice cycles are used to program the zr36060, or the zr36050 and zr36016. 5.3.1 flexible guestbus timing different guest devices may have different bus timing require- ments. in order to meet these requirements and still master the guestbus efficiently, the zr36067-lv has two timing parame- ters for each guest: t gdurn is the duration of a gwr or grd signal when accessing guest n. t grecn is the minimum recovery time in which grd and gwr must be non active after the rising edge of the previous access (read or write) to guest n. t gdur and t grec are configured by the host in units of pci clock (3,4,12 or 15 pci clocks are the possible values). additional timing parameters are given in section 15.0 ac timing specifications. 5.3.2 code-write operations code-write cycles are initiated by the guestbus master if all of the conditions below are met: ? the cfifo is not empty. ? a postoffice request is not pending. ? the grdy input is high (1). a code-write cycle consists of reading one code byte from the cfifo and writing it to the guest selected by the host for code- write cycles, to the register address configured by the host. the timing parameters of the code-write cycle are those pro- grammed by the host for this specific guest device. note that the same parameters apply for postoffice accesses to this guest. 5.3.3 doubleword to bytes mapping in code-write operations the code is read in doublewords from main memory, and trans- ferred in bytes to the guest device. the ordering of the bytes is such that the least significant byte of the doubleword is the first one to be sent over the guestbus, and the most significant byte is the last one. 5.3.4 postoffice operations when the postoffice pending bit (popen) in the postoffice register is set to 1, the guestbus master completes the current code-write cycle (if such is executed), and executes a postoffice cycle, even when the code fifo is not empty. the type of the cycle (read or write) is determined by the postoffice direction bit (podir). the identity of the targeted guest and its specific register are also specified by the postoffice register. in both read and write cycles the timing parameters of the cycle are those configured by the host for the targeted guest. upon com- pletion of a postoffice cycle, the pending bit is reset to 0 by the zr36067-lv. postoffice write: the guestbus master transfers the least sig- nificant 8 bits of the postoffice register out on the bus. postoffice read: the guestbus master reads from the specified target and writes the input byte into the least significant 8 bits of the postoffice register (podata) 5.3.5 guestbus wait states slow guests that are equipped with a bus hold output can force a code-write or postoffice guestbus cycle to be extended by one or more additional pci clocks, by asserting the gws signal. gws is first sampled with the pci clock that precedes the one that triggers the de-assertion of gwr or grd (if t gdur of the accessed guest is m pci clocks, gws is sampled m-1 clocks after the assertion of gwr or grd ). when gws is sampled high again, the cycle is completed. insertion of wait states is possible during both code-write and postoffice cycles. the maximum number of pci clock cycles allowed for grd or gwr , including wait-states, is 64. if a guest holds the cycle until this limit expires, the guestbus master aborts the cycle. if the cycle was a postoffice one, the postoffice time-out bit of the postoffice register is set to 1, and the postoffice pending bit is cleared. if the cycle was a code-write (or code-read, if viewed from the pci side), the code-write time-out flag (codtime) is set to 1. figure shows two examples of guestbus cycles. the upper one is a write to guest 0, register 0, followed by a read from guest 0, register 5. note that for guest 0 t gdur0 =3 and t grec0 =4. the lower 2. a typical choice for guest configured a priori for the code-write cycles would be a decompression device, such as the zr36110 or zr36700, in the zr36067-lvs mpeg mode. 15 enhanced pci bus multimedia controller (low-voltage) example shows a read from guest 2, register 1, with 3 wait-states inserted by the guest. notice that the assertions of gadr and gcs are done together. the assertion of grd and gwr is done one pci clock after the assertion of gadr and gcs . the de-assertion of grd and gwr is done one pci clock before the de-assertion of gadr and gcs . 5.4 postoffice handshaking protocol reading data from or writing data to any of the zr36067-lv guests using the postoffice mechanism requires the host software to follow the handshaking protocol described below. the main idea is that the host has to poll the postoffice request pending bit in order to confirm the availability of the guestbus and verify the validity of the data contained in the postoffice data byte. in general, host accesses to the postoffice register may change the postoffice pending bit, as explained below. thus, the host software must ensure that accesses to the postoffice register are governed by a central routine. for example, inde- pendent accesses to the postoffice register both from an interrupt service routine and the main processor task(s), or from more than one task in a multitasking environment, might cause a deadlock, unless explicit protection measures are taken. 5.4.1 host writes to a guest device ? the host reads the postoffice register, and checks the post- office pending bit. if this bit is 1, the write cycle cannot be executed now, because the guestbus master is busy exe- cuting a previous postoffice read or write request. once this bit is 0, the write request can be made. ? the host writes a full doubleword to the postoffice register, containing the data byte to be sent to the guest, the guests identity (0,...,7), the specific guest register (0,...,7), and an indication that this is a write request (direction bit = 1). as a result of writing to the postoffice data byte, the postoffice pending bit is set to 1. ? the zr36067-lv completes the current code-write cycle, if one is being executed, and, before executing the next code- write cycle (if one is needed), it executes the pending post- office request. at the completion of the guestbus write cycle it clears the request pending bit. ? the host may read the postoffice register, to verify that the pending bit is 0, meaning that the write request has been completed. ? note that in multiple (back-to-back) postoffice operations the host has to poll the request pending bit only once be- tween two requests, since reading this bit zero indicates pci clk example 2 gcs0 12345678910111213 gadr[2:0] 0x0 0x5 gwr grd gws gdat[7:0] pci clk gcs2 12345678910111213 gadr[2:0] 0x1 gwr grd gws gdat[7:0] example 1 sampling points figure 4. two examples of guestbus cycles data valid from zr36067-lv data valid from guest 16 enhanced pci bus multimedia controller (low-voltage) both that the previous request has been completed and that the next request can be made. 5.4.2 host reads from a guest device ? the host reads the postoffice register, and checks the post- office pending bit. if this bit is 1, the read cycle cannot be executed now, because the guestbus master is busy exe- cuting a previous postoffice read or write request. once this bit is 0, the read request can be made. ? the host writes a full doubleword to the postoffice register, containing the guests identity (0,..,7), the specific guest reg- ister (0,...,7), and an indication that this is a read request (direction bit = 0). the data portion of the doubleword is meaningless, but should be set to a byte of zeros. as a result of writing to the postoffice data byte, the postoffice pending bit is set to 1. ? the zr36067-lv completes the current code-write cycle, if one is being executed, and before executing the next code- write cycle (if one is needed), it executes the pending post- office request. it transfers the byte read from the guest to bits 7...0 of the postoffice register. at the completion of the guestbus read cycle it clears the request pending bit. ? the host may read the postoffice register, to verify that the pending bit is 0, meaning that the read request has been completed and the data portion of the postoffice register is the result. ? note that in multiple (back-to-back) postoffice operations the host has to poll the request pending bit only once be- tween two requests, since reading this bit zero indicates both that the previous request has been completed and that the next request can be made. 5.5 codec bus interface the codec front end (cfe) interfaces to the zr36060 or zr36050 jpeg codec to transfer code (compressed data) to or from the zr36067-lv. the cfe is designed to operate with the zr36060 or zr36050 configured in code bus master mode. in compression mode, the cfe receives the code stream from the codec and transfers it to the code fifo. in decompression mode, the cfe transfers the code stream from the code fifo to the codec in response to the codecs read requests. the cfe uses the code[7..0] bus to transfer the code using the handshaking signals ccs and cbusy , synchronized to vclkx2. the zr36067-lv supports the highest zr36060 and zr36050 code bus transfer rate, one clock cycle per code bus cycle. 5.5.1 compression mode code transactions the functional timing diagram for compression is shown in figure 5. in this example, two code bytes are transferred from the zr36060 to the zr36067-lv. the falling edge of ccs desig- nates the start of the cycle. the data is driven by the zr36060 at the rising edge of vclkx2. the zr36067-lvs codec inter- face samples the data with vclkx2 enabled by ccs . 5.5.2 decompression mode code transactions the functional timing diagram for decompression is shown in figure 6. in this example, two code bytes are transferred from the zr36067-lv to the zr36060. the falling edge of ccs desig- nates the start of the cycle. the data is driven by the zr36067- lv. the zr36060 samples the data with the rising edge of coe (note that coe is not an input to the zr36067-lv; it is men- tioned here only for the completeness of the description). 5.5.3 code bus stalling the zr36060 is the master of the code transactions in compres- sion and decompression modes. any number of bytes can be transferred in a contiguous burst. the zr36067-lv uses the zr36060s cbusy signal to stall the code bus, in order to prevent overflow of the code fifo in compression or underflow in decompression. figure 7 shows the functional timing diagram for code bus stalling. the zr36060 examines cbusy one clock cycle prior to the beginning of each access cycle. the zr36067-lv asserts vclkx2 ccs code[7:0] (input) n figure 5. compression mode code transactions n+1 vclkx2 ccs code[7:0] (output) n figure 6. decompression mode code transactions n+1 coe (not an input to the zr36067-lv) 17 enhanced pci bus multimedia controller (low-voltage) cbusy one vclkx2 cycle before the beginning of the last desired code transfer cycle. 5.5.4 connecting zr36067-lv to zr36060 host and code interfaces figure 8 shows the recommended connection of the zr36067- lv to the zr36060 host and code interfaces. for recommend- ed connections between the zr36067-lv and the zr36050 host and code interfaces, refer to the zr36057 data sheet. 5.5.4.1 zr36060 host interface the host interface of the zr36060 is controlled by the zr36067- lv as one of the guests. the recommended guest timing param- eters are tdur=12, trec=3. 5.5.4.2 cend input signal assertion of end by the zr36050 indicates the end of a field process in compression or decompression. this is latched as cend in the codec interface. 5.5.4.3 the zr36060 start signal start signals the zr36060 to start a compression or decom- pression process. activation of start is performed automatically by the zr36067-lv, by writing to a guest designat- ed for this purpose (specified by jpeguestid ). in motion video compression mode, the first activation of start is initiated by the host after finishing the initialization of all the peripheral devices. after completion of the first field, start is activated by the zr36067-lv after the code of the previous field has been transferred to system memory. in decompression mode, start is activated only after the code fifo has been filled from the relevant system memory code buffer. 5.5.4.4 ccs input signal the zr36060s ccs signal designates the start of a code trans- action. it stays active until the end of the transaction. in compression mode, the zr36067-lv uses ccs to enable the sampling of the incoming code stream. in decompression mode, it uses ccs to enable the drive of the code stream. 5.6 i2c bus interface the i 2 c port of the zr36067-lv consists of a clock signal, sck, and data signal, sda. both have two possible levels: active low or passive tri-state. this configuration lets the zr36067-lv be the only master of an i 2 c clock. both lines must be pulled-up externally. by accessing the i 2 c application-specific register bits appropriately, the host software can generate valid i 2 c start and stop conditions, write address and write or read data one bit at a time. 5.7 general purpose i/o pins the zr36067-lv has 8 general purpose i/o pins, fully controlled by the host. each of these pins can be separately configured as input or output. when configured as an output, the host is able to force the level of a pin through its corresponding register bit. 5.8 interrupt requests the zr36067-lvs interrupt manager connects to the various conditions that may generate an interrupt request, enables or disables them as specified in the interrupt control register, and drives the inta output. it stores the corresponding status bits in the interrupt status register, and clears the status bits per host instructions. the zr36067-lv can associate any one of the following events with an interrupt request: ? a positive edge on the girq1 input pin. ? a positive edge on the girq0 input pin. ? mpeg mode - the code memory buffer pointer passing one of its report points. ? jpeg modes - successful completion of a jpeg field or frame process (in compression or decompression). each of these events can be separately enabled or disabled through the corresponding bit in the interrupt control register. an additional global enable bit enables or disables all interrupts. when an interrupt-associated event occurs, two things happen: vclkx2 ccs code[7:0] figure 7. code bus stalling coe / cwe cbusy this access is blocked. figure 8. zr36067-lv and zr36050 host and code ccs cbusy end code[7:0] addr[1:0] data[7:0] cs rd wr reset ccs cbusy cend code[7:0] gdat[7:0] gadr[1:0] gcsn grd gwr gpioa zr36060 zr36067-lv sleep gpiob frame gpioc start gcsm 18 enhanced pci bus multimedia controller (low-voltage) ? the corresponding bit in the interrupt status register is set. ? if the interrupt is enabled, and the interrupts are enabled glo- bally, the inta open-drain output pin is asserted to its active-low level. both the status bit(s) and inta remain active, until the host clears those status bits that are currently set. this is done by writing a 1 to those bits. when the host does that, the inta output signal returns to its passive, tri-state level. if the host attempts to clear any of the interrupt status register bits at the same time that the interrupt logic attempts to set it (because of an interrupt event), the set operation has priority over the clear operation. 19 enhanced pci bus multimedia controller (low-voltage) 6.0 video input processor 6.1 horizontal filter prior to a significant horizontal down scaling of the input image, it is advisable to apply one of the possible horizontal filters. the filter type is selected through the hfilter parameter. 6.2 horizontal/vertical downscaler the horizontal and vertical down scalers are independent of each other. the horizontal scaling ratio is configured through the hordcm parameter. hordcm indicates the number of pixels to drop out of every 64 consecutive pixels. hordcm ranges from 0 to 63, where 0 represents the no scaling configuration (1:1 input to output ratio). the vertical scaling ratio is configured through the verdcm parameter. verdcm indicates the number of lines to drop out of every 64 consecutive lines. verdcm ranges from 0 to 63, where 0 represents the no scaling configuration (1:1 input to output ratio). the vertical downscaler can operate in two ways. if dupfld=0 it treats the top and bottom fields the same way. if dupfld=1 it uses different line dropping topologies for the top and the bottom fields, such that if the fields are equal (one field is actually dupli- cated, like the output of most mpeg-1 decoders), then the total loss of information is minimized. for example, when the video source is a video decoder, it is recommended to apply dup- fld=0, and when the video source is the zr36110, and the ccir size is down scaled by half or more, it is recommended to apply dupfld=1. 6.3 color space converter the color space converter converts the yuv input to rgb format. the yuv2rgb parameter determines the type of conversion: when the 15- or 16-bit rgb format is selected, it is advisable to apply the error diffusion option, in order to eliminate false contours from the output image. this option is selected by the errdif parameter (1 turns the error diffusion option on, while 0 turns it off). hfilter = 0 filter 1: no luminance filter, 3-tap pre-interpolation filter of chrominance. hfilter = 1 filter 2: 3-tap luminance filter, 3-tap pre-interpolation chrominance filter. hfilter = 2 filter 3: 4-tap luminance filter, 4-tap chrominance filter. hfilter = 3 filter 4: 5-tap luminance filter, 4-tap chrominance filter. hfilter = 4 filter 5: 4-tap luminance filter, 4-tap chrominance filter. yuv2rgb = 00b no conversion, output format is yuv 422. yuv2rgb = 01b conversion to rgb 8,8,8 (24-bit output) yuv2rgb = 10b conversion to rgb 5,6,5 (16-bit) yuv2rgb = 11b conversion to rgb 5,5,5 (15-bit) 20 enhanced pci bus multimedia controller (low-voltage) 7.0 video output control the zr36067-lv outputs the video pixels over the pci bus, using dma bursts, initiated and controlled by the zr36067-lvs video dma controller. in order to enable the dma controller, the master enable bit of the pci configuration space must be set to 1, and the viden bit in the video display configuration register must also be set to 1. once viden==1, the software is not allowed to change registered parameters that are involved in the video processing. the register description (see applica- tion-specific registers (asrs) on page 26) specifies the conditions under which each parameter is allowed to be modified. the zr36067-lv transfers the video to a rectangle in the display (or system) memory, defined by a base address for each field (masktopbase, maskbotbase), an inter-line stride (dispstride), and the rectangle height (vidwinht) and width (vidwinwid). obviously, these parameters must be provided by the host prior to enabling the video dma controller. 7.1 display modes the zr36067-lv can either display both fields, emulating the interlaced input, or only the top field. the latter option has the advantage of reducing the motion artifacts that might be exhibit- ed when interlaced video is displayed on a non-interlaced monitor. the parameter that controls the display mode is dispmod. by a proper configuration of the display base addresses it is also possible to display two fields (from either one or two separate video sources) on two separate rectangles (video windows). 7.2 frame grabbing the zr36067-lv has a special mode for capturing video frames (or fields) and storing them in system memory. this mode is invoked by setting the snapshot parameter to 1. when in this mode, every time the host switches the framegrab bit from 0 to 1, the zr36067-lv downloads a frame (or a field, if disp- mod==1), to memory. following is an example of a flow of actions intended to grab one frame. the example assumes that the vertical sync is used as an interrupt source (by externally tying vsync to girq0 or girq1), and that prior to grabbing the frame, the zr36067-lv operates in the normal continuous scheme of live video display. ? through a push-button click in the application gui the user triggers a frame grabbing request. ? the host sets snapshot=1. the zr36067-lvs video dma controller waits for the next vsync and then freezes the live display. since now snapshot=1 and framgrab=0, video parameters can be changed (even without viden=0; refer to section 13.0 application-specific registers (asrs)). ? the host sets new addresses in vidtopbase and vidbot- base. these addresses point to main memory. dispstride is also given a new value. if needed, other video parameters can be changed now, e.g., pixel format, etc. ? the host sets framegrab=1. the zr36067-lv waits until the next vsync and then transmits two consecutive fields to main memory. ? after the second of the two fields is completed, framegrab is cleared by the zr36067-lv. ? when the host senses (after constant polling or polling in- side vsync-triggered interrupts) that framegrab=0 again, it sets the old addresses back to vidtopbase and vidbot- base. dispstride is given back its old value. the remainder of the previous video parameters can be restored now. ? the host sets snapshot=0, putting the zr36067-lv back into the continuous video display mode. ? with the next vsync the zr36067-lvs video dma con- troller resumes normal live display operation. 7.3 output pixel organization the output pixel format is determined by the following parame- ters: yuv2rgb, pack24 (applicable only to rgb 8,8,8 format), and littleendian (applicable to all formats, excluding the 24-bit packed). following are the bit organizations of the different pixel formats when a video doubleword is transferred over the pci bus: table 4: yuv 4:2:2 pixel format endian-ness bits 31...24 23...16 15...8 7...0 little endian y17...0 v07...0 y07...0 u07...0 gib endian v07...0 y17...0 u07...0 y07...0 table 5: rgb 5,5,5 pixel format endian-ness bits 31...24 23...16 15...8 7...0 little endian 0,r14...0, g14...3 g12...0, b14...0 0,r04...0, g04...3 g02...0, b04...0 gib endian g12...0, b14...0 0,r14...0, g14...3 g02...0, b04...0 0,r04...0, g04...3 table 6: rgb 5,6,5 pixel format endian-ness bits 31...24 23...16 15...8 7...0 little endian r14...0, g15...3 g12...0, b14...0 r04...0, g05...3 g02...0, b04...0 gib endian g12...0, b14...0 r14...0, g15...3 g02...0, b04...0 r04...0, g05...3 21 enhanced pci bus multimedia controller (low-voltage) in the 24-bit packed format the first active pixel in a line is always packed as indicated in the first row of table 8. from then on the byte organization is as described by the table. 8.0 graphics overlay the zr36067-lvs video dma controller is capable of masking off (i.e., not transmitting) pixels that are marked by 0 in a masking map prepared and maintained by the driver software. the masking feature, referred to as overlay or clipping, is turned on by setting the ovlenable parameter to 1. as long as ovlen- able=0, all pixels within the selected portion of the image are transferred to destination. the masking map is a one bit deep map of the video rectangle. its location in system memory is defined by a pair of base addresses (one for each field - mask- topbase, maskbotbase), and an inter-line stride (maskstride). the width of the map must be doubleword aligned. thus, the line size is: int((vidwinwid+31) >> 5) and the number of lines in the map is: 2*vidwinht, if dispmod==0, or vidwinht, if dispmod==1. in order to match the 0/1 values of the map to their correspond- ing pixels in the video rectangle, the map must follow the format given in table 9. 9.0 jpeg code transfer the data flow direction depends on the jpeg mode of opera- tion. in motion video and still image compression, the code is transferred from the code bus to the system memory. in motion video and still image decompression, the code is transferred from the system memory to the code bus. the compressed data in system memory is structured within code buffers. each code buffer may contain a compressed field or frame (two fields) as specified by a user-configurable bit. the zr36067-lv supports four code buffers, defined dynamical- ly in a dedicated table, the code buffer table, in the system memory. before starting a new jpeg process, the host must load the physical address of the code buffer table into the i_stat_com_ptr register of the zr36067-lv. the actual memory allocated to each code buffer by the operat- ing system may be fragmented. the content of each entry in the code buffer table is a pointer to a secondary fragment table. the fragment table contains the pointers to the allocated memory chunks. figure 9 provides a graphical description of the data structure in the system memory. 9.1 the code buffer table the code buffer table consists of four stat_com (status or command) entries, one for each code buffer. the interpretation of each stat_com entry is determined by its l.s. bit, the stat_bit. if stat_bit=0, the content of the entry is the com- table 7: 24-bit unpacked pixel format endian-ness bits 31...24 23...16 15...8 7...0 little endian 0x0 r7...0 g7...0 b7...0 gib endian b7...0 g7...0 r7...0 0x0 table 8: 24-bit packed pixel format bus cycle bits 31...24 23...16 15...8 7...0 first b17...0 r07...0 g07...0 b07...0 second g27...0 b27...0 r17...0 g17...0 third r37...0 g37...0 b37...0 r27...0 table 9: bit, byte and doubleword organization of the masking map dword ...1 0 byte ...03210 bit 7....0 31...24 23...16 15... 8 7...0 pixel index in line 39...32 31...24 23...16 15...8 7...0 figure 9. jpeg code data structure in system memory i_stat_com_ptr address_0 fragment table length_0 address_1 address_n-1 f length_1 f length_n-1 f f=final code buffer table stat_com0 stat_com1 stat_com2 stat_com3 fragment_0 fragment_1 fragment_n-1 22 enhanced pci bus multimedia controller (low-voltage) mand information, written by the host, for the next available buffer. table 10 shows the interpretation for this case. if the stat_bit=1, the content of the entry is the status infor- mation, written by the zr36067-lv, of the most recently processed field or frame. table 11 shows the interpretation for this case. 9.2 fragment table the fragment table (figure 9) defines the structure of the allo- cated memory for each code buffer. the table has n entries for n allocated fragments. each entry holds two doublewords: ? first doubleword - the physical address of the fragment (must be doubleword aligned). ? second doubleword - has the following fields: - bits 20:1, the fragment length in doublewords (the frag- ment must be doubleword aligned), - bit 0, f (final bit), when 1 indicates that this fragment is the final fragment of the buffer, - bits 31:21, unused, must be 0. 9.3 jpeg compression modes the sequence of actions performed by the host software and the zr36067-lv is as follows: ? the host allocates the first four code buffers and writes out the code buffer table and the fragment table. ? the host loads the zr36067-lvs i_stat_com_ptr regis- ter with the base address of the code buffer table. ? after the start of the compression process, the zr36067-lv starts filling the fragments of the first code buffer with the compressed data of the first field or frame. ? after successfully completing transfer of the compressed data of a field or frame, the zr36067-lv writes the status in- formation back to the stat_com entry of the current buffer. it sets the status_bit in the stat_com entry, declaring its content as status. it then issues an interrupt, and starts the next field or frame process. ? if a new code buffer is unavailable at the beginning of a field or frame process (that is, if the status_bit of the next buffer entry is 1), the zr36067-lv polls the stat_com entry until the buffer is available. ? when the host receives the interrupt, it checks the stat_com entries in the code buffer table. for each entry whose stat_bit=1, the host checks f_cnt to determine whether any fields/frames were dropped. it records the code buffer information, updates the fragment table and stat_com entry of the code buffer, and returns it by reset- ting stat_bit to 0. several scenarios might cause a field or frame process to be unsuccessful: ? the allocated code buffer memory was smaller than the ac- tual field/frame code volume (the zr36067-lv fills the final fragment, but the field/frame code transfer is not complete). ? a zr36060 strip memory overflow occurs during the field/ frame compression (might be caused by very large pci bus latency). ? the compression of a field has not ended by the time the trailing edge of the next vsync is detected. after an unsuccessful field/frame process in compression, the zr36067-lv does not issue an interrupt, re-uses the current code buffer - that is, does not over-write its stat_com entry, and restarts with the next field or frame. the software can deter- mine the number of fields or frames that were skipped by reading f_cnt. 9.4 jpeg decompression modes the sequence of actions performed by the host software and the zr36067-lv is as follows: ? the host allocates the first four code buffers and writes out the code buffer table and the fragment table. ? the host fills the allocated fragments with the code to be decompressed. ? the host loads the zr36067-lvs i_stat_com_ptr regis- ter with the base address of the code buffer table. table 10: stat_com entry content, when stat_bit=0 bit content description 31:2 frag_tab_ptr[31:2] the address pointer to the fragment table of the next buffer to be used. the 2 l.s. bits of the address must be 0 - that is, the address must be doubleword aligned. 1 frag_tab_ptr [1] must to be 0. 0 stat_bit must be 0 to indicate that the table entry is a command. table 11: stat_com entry content, when stat_bit=1 bit content description 31:24 f_cnt[7:0] the serial number, modulo 256, of the most recent field or frame. used in compression only. 23 reserved, set to 0. 22:1 f_length[21:0] the length of the most recently com- pressed field or frame in bytes, used in compression only. the length is dou- bleword aligned, so bits 2..1 are always 0. 0 stat_bit 1, indicating that this table entry is a status written by the zr36067-lv. 23 enhanced pci bus multimedia controller (low-voltage) ? after the start of the decompression process, the zr36067- lv starts reading the code of the first field or frame from the code buffer fragments. ? after completing decompression of the field or frame, the zr36067-lv sets the status_bit in the stat_com reg- ister, declaring that this buffer was already decompressed, issues an interrupt, and starts the next field/frame process. it reads the next stat_com entry from the code buffer table. if the buffer is available, that is, the stat_bit=0 indicating it contains the code of a new field/frame, the zr36067-lv starts transferring its fragments for decompression. ? if a new code buffer is unavailable at the beginning of a field or frame process (that is, if the status_bit of the next buffer entry is 1), the zr36067-lv repeats decompression of the last available code buffer. ? when the host receives the interrupt, it checks the stat_com entries in the code buffer table. for each entry whose stat_bit=1, the host loads compressed data into a new code buffer and updates its fragment table, then re- turns the buffer by resetting its stat_bit to 0. 10.0 reset there are three means of resetting the zr36067-lv. one is a hardware reset, which is applied through the pcirst input, the second is a software reset, which is applied through the softre- set register bit. the third is the jpeg process reset asserted by the p_reset register bit. 10.1 hardware reset the hardware reset signal pcirst resets the internal state machines in the zr36067-lv and loads all registers with their default states. the reset state of the pci interface pins is as defined by the pci specifications (2.1). the reset state of the other output/bidirectional signals is as follows. the gpio[7:0] lines are all inputs after reset. if required for system purposes, they can be pulled high or low through 1 k external resistors to have fixed values on reset. as long as pcirst is asserted, the following signals are tri- stated: gdat[7:0], gadr[2:0], gcs [3:0], gwr , grd , sda, scl. once the pcirst input is deasserted, these signals go to their software reset condition (as does the entire device). a hardware reset asserts (clears) the softreset bit in the system register. after the hardware reset is over, the zr36067-lv will be in software reset condition until the softreset bit is deasserted. 10.2 software reset there are two ways in which the zr36067-lv can go into the software reset condition: one is right after hardware reset (i.e., upon the low to high transition of pcirst ), the other is by clearing the softreset bit. while in software reset, all registers and state machines in the device are reset to their default values/states, except the soft- reset bit itself, and the pci interface (including the pci configuration space registers). the device continues to respond according to the pci specifica- tion and can be the target of a pci transfer targeted at the asrs (application specific registers) or pci configuration space. while in software reset the device will not initiate any pci trans- fers, because all dma channels are disabled. after the softreset bit is deasserted, all registers retain their default values, all dma channels remain disabled and all asrs are programmable according to their normal modification conditions. hence, the initialization of the device (loading all registers with the values required for the specific application) must start with setting softreset to 1, otherwise new asr values will not be latched in. 10.3 jpeg p_reset the p_reset bit resets all of the jpeg related state machines and controls in the zr36067-lv. the p_reset bit enables re-configuration of all jpeg parameters with no effect on the other functions of the device. before starting a new jpeg process, and while loading new jpeg parameters, the p_reset bit must be asserted. 24 enhanced pci bus multimedia controller (low-voltage) 11.0 subsystem id and subsystem vendor id the subsystem id and subsystem vendor id registers are con- figured at pci reset time. immediately after the trailing edge of pcirst , the zr36067-lv latches the current state on 32 of its input pins into these registers. thus, if the system design takes this into consideration and ensures that the relevant pins are not being driven by any other device at the trailing edge of pcirst , the required states can be assigned to the pins by means of pull- up or pull-down resistors. note: to ensure that the states of the pins are latched correctly, they must remain stable for at least 3 pci clock periods after the trailing edge of pcirst . 11.1 subsystem id the pins used to configure the subsystem id are shown in table 12. 11.2 subsystem vendor id the pins used to configure the subsystem vendor id are shown in table 13. table 12: signal pins used for subsystem id subsystem id bit signal pin 15 gpio7 14 gpio6 13 gpio5 12 gpio4 11 gpio3 10 gpio2 9gpio1 8gpio0 7uv/g7 6uv/g6 5uv/g5 4uv/g4 3uv/g3 2uv/g2 1uv/g1 0uv/g0 table 13: signal pins used for subsystem vendor id subsystem vendor id bit signal pin 15 gdat7 14 gdat6 13 gdat5 12 gdat4 11 gdat3 10 gdat2 9gdat1 8gdat0 7y/r7 6y/r6 5y/r5 4y/r4 3y/r3 2y/r2 1y/r1 0y/r0 25 enhanced pci bus multimedia controller (low-voltage) 12.0 pci configuration space registers the pci specification requires that a pci device include a con- figuration register space, a set of 256 8-bit configuration registers. the first 64 bytes make up the configuration header, predefined by the specification and the remainder are applica- tion specific. these registers allow device relocation, device independent system address map construction and automatic configurations. how the configuration registers are accessed by the host software is platform dependent; the host pci bridge is responsible for translating the host accesses to a pci configura- tion cycle, including the assertion of the idsel input. the zr36067-lv then responds to these cycles. this section details the zr36067-lvs pci configuration registers. pci configuration accesses to zr36067-lv configuration addresses that are not explicitly described here return zeros (in reads). table 14: zr36067-lv pci configuration space registers address offset bits type description 0x00 31:16 r device id. hardwired to 0x6057. 15:0 r vendor id. hardwired to 0x11de. 0x04 31 rc parity error detected. this bit is set when a parity error is detected, regardless of the parity error response bit. 30 r system error signaled. hardwired to 0. 29 rc master abort detected. this bit is set when a master-abort condition has been detected. 28 rc target abort detected. this bit is set when a target-abort condition has been detected. 27 rc target abort signaled. when the zr36067 terminates a transaction as a target (e.g., due to wrong address parity) it sets this bit. 26:25 r devsel timing. hardwired to 00 (fast timing, i.e., devsel is asserted before rising edge of clock three within a cycle). 24 r data parity reported. hardwired to 0. 23 r fast back-to-back capability. hardwired to 0. 22:16 r reserved. returns zeros. 15:10 r reserved. returns zeros. 9 r fast back-to-back enable. hardwired to 0. 8 r system error enable. hardwired to 0. 7 r wait cycle (stepping) enable. hardwired to 0. 6 r parity error response. hardwired to 0. 5:3 r unused. hardwired to 0. 2 rw master enable. when this bit is set to 1 the zr36067-lv can operate as a bus master. default is 0. 1 rw memory access enable. when this bit is set to one the device responds to pci memory accesses. default value is 0. 0 r i/o access enable. hardwired to 0. 0x08 31:8 r class code. returns 0x040000 (multimedia video device) 7:0 r revision id. hardwired to 0x02 0x0c 31:24 r unused. return zeros. 23:16 r header type. returns zeros. 15:8 rw master latency timer. the number of pci clocks that limit zr36067-lv-initiated bursts in case gnt is deasserted by the bus arbiter during the zr36067-lv-initiated burst. the 3 ls bits are read-only zeros. the default value is 0x00. 7:0 r unused. returns zeros. 0x10 31:12 11:0 rw r memory base address. this value determines the base address of the zr36067-lv as a memory- mapped device. the zr36067-lv occupies a range of 4096 bytes out of the memory map: bits 11:0 are hardwired to 0. the default value of all other bits is 0. 0x14 to 0x2b r hardwired to 0. 0x2c 31:16 r subsystem id. see section 11.1 15:0 r subsystem vendor id. see section 11.2 0x30 to 0x3b r hardwired to 0. 26 enhanced pci bus multimedia controller (low-voltage) 13.0 application-specific registers (asrs) the zr36067-lv application-specific registers (asrs) are memory-mapped. their base address is configured by the host into pci configuration address 0x10. the zr36067-lv claims a contiguous range of 4k bytes of memory. pci memory-read accesses to addresses (within the 4k range) that are not explic- itly described in this section return zeros. the asrs can be accessed in any byte combination. the column mod of the following tables defines the conditions under which each parameter of the asrs is allowed to be modified by the host software. the following abbreviations are used: note that after a hard or soft reset viden = 0, codreaden = 0, and p_reset = 1. 13.1 video front end horizontal configuration register this 32 bit register contains the horizontal configuration param- eters of the video source. 13.2 video front end vertical configuration register this 32 bit register contains the vertical configuration parame- ters of the video source. 0x3c 31:24 r max_lat - hardwired to 0x10 (i.e., 4 s). this value indicates for the operating system how often the device needs access to the pci bus. 23:16 r min_gnt - hardwired to 0x2 (i.e., 0.5us). indicates to the operating system the minimum length of a burst. 15:8 r interrupt pin. hardwired to 0x1, indicating that inta is used. 7:0 rw interrupt line. these bits indicate the interrupt line that is being used (e.g., irq10 => 0xa, etc.). default value is 0xa. table 14: zr36067-lv pci configuration space registers (continued) address offset bits type description abbreviation description all this parameter may be modified on the fly, i.e. any time. res this parameter is set once after a reset of the zr36067-lv, no modifications allowed during operation. vid this parameter may be modified if either viden = 0 or snapshot = 1 and framegrab = 0. cod this parameter may be modified if codreaden = 0. snap this parameter may be modified if snapshot = 1. jpg this parameter may be modified if p_reset = 0. address offset: 0x000 bit type mod description 31 r reserved. returns zero. 30 rw vid hspol - hsync polarity. hstart and hend are counted from the active edge of hsync. 1 - negative edge of hsync. 0 - positive edge of hsync (default value). hspol also determines hsync polarity when syncmstr =1. 29:20 r reserved. returns zero. 19:10 rw vid hstart - horizontal start offset. number of pixel clocks in a line from the active edge of hsync until the first pixel to be sampled. default value is 0x001. 9:0 rw vid hend - horizontal end offset. number of pixel clocks in a line from the active edge of hsync until the last pixel to be sampled. default value is 0x3ff. address offset: 0x004 bit type mod description 31 r reserved. returns zero. 30 rw vid vspol - vsync polarity. vstart and vend are counted from the active edge of vsync. 1 - negative edge of vsync. 0 - positive edge of vsync (default value). vspol also determines vsync polarity when syncmstr =1. 29:20 r reserved. returns zero. 19:10 rw vid vstart - vertical start offset. number of lines from the active edge of vsync until the first line to be sampled. default value is 0x001. 9:0 rw vid vend - vertical end offset. number of lines from the active edge of vsync until the last line to be sampled. default value is 0x3ff. address offset: 0x000 (continued) bit type mod description 27 enhanced pci bus multimedia controller (low-voltage) 13.3 video front end, scaler and pixel format register this register contains the video front end configuration (byte 3), video scaler (bytes 2-1) and pixel formatter (byte 0) parameters address offset: 0x008 bit type mod description 31:27 r reserved. returns zero. 26 rw vid extfi - external field indication. 1 - the video source provides an fi signal. 0 - field indication is derived from hsync and vsync (default value). 25 rw vid topfield - top field interpretation. if field indication is derived from the fi input signal (see extfi), then this parameter defines which level of fi indicates the top field: 1 - fi high indicates the top field (default value). 0 - fi low indicates the top field. if field indication is derived internally from hsync and vsync, then this parameter defines which level of hsync indicates the top field on the active edge of vsync: 1 - hsync high indicates the top field (default value). 0 - hsync low indicates the top field. 24 rw vid vclkpol - video clock polarity. when set to 0 (default value), the video interface inputs are sampled by the positive edge of vclkx2 that is qualified by vclk = 0. the video interface outputs (other than pxen ) are driven at the negative edge of vclkx2 which is qualified by vclk = 1. when set to 1, the video interface inputs are sampled by the positive edge of vclkx2 that is qualified by vclk = 1. the video interface outputs (other than pxen ) are driven at the negative edge of vclkx2 which is qualified by vclk = 0. 23:21 rw vid hfilter - horizontal filter selection. the following horizontal filters can be selected: 000b - filter 1 = no luminance, 3-tap chrominance 001b - filter 2 = 3-tap luminance, 3-tap chrominance 010b - filter 3 = 4-tap luminance, 4-tap chrominance 011b - filter 4 = 5-tap luminance, 4-tap chrominance 100b - filter 5 = 4-tap luminance, 4-tap chrominance 101b - 111b will result in the default filter. default value 000b. 20 rw vid dupfld - duplicate field. this parameter has an effect on the vertical decimation of a frame in respect to the video source. the result is less loss of information and less distortion. 1 - indicates top and bottom fields are equal. 0 - indicates an interlaced video source, top and bottom fields are different (default value). 19:14 rw vid hordcm - horizontal decimation ratio. this parameter defines the number of pixels to be dropped out of every 64 consecutive pixels. 000000b - no horizontal decimation (default value). 13:8 rw vid verdcm - vertical decimation ratio. this parameter defines the number of lines to be dropped out of every 64 consecutive lines. 000000b - no vertical decimation (default value). 7 r reserved. returns zero. 6rwvid dispmod - display mode. 1 - single field. 0 - emulated interlaced video (default value). 5 r reserved. returns zero. 4:3 rw vid yuv2rgb - yuv to rgb conversion. this parameter defines the pixel output format: 00b - yuv 4:2:2, 01b - rgb 8,8,8, 10b - rgb 5,6,5 (default value), 11b - rgb 5,5,5. 2rwvid errdif - error diffusion. this parameter has an effect only on rgb 5,6,5 and 5,5,5 output formats. 1 - error diffusion is active 0 - simple truncation of rgb 8,8,8 is executed (default value). 1rwvid pack24 - 24 bit packed format. this bit is applicable only if yuv2rgb = 01b. 1 - rgb 8,8,8 is packed such that it takes 3 pci cycles to transfer 4 pixels. 0 - one pixel per pci cycle is transferred (default value). 0rwvid littleendian - little endian format flag. 1 - pixel layout on pci is little endian (default value). 0 - pixel layout on pci is gib endian. address offset: 0x008 (continued) bit type mod description 28 enhanced pci bus multimedia controller (low-voltage) 13.4 video display top register this register contains the doubleword base address of the top field. 13.5 video display bottom register this register contains the doubleword base address of the bottom field. 13.6 video stride, status and frame grab register this register contains parameters for display addressing (bytes 2-3), status of vfifo (byte 1) and frame grab control (byte 0). 13.7 video display configuration register this register contains the configuration parameters for the video display. address offset: 0x00c bit type mod description 31:2 1:0 rw r vid vidtopbase - video top field base address. this is the destination starting address for the top field. default value is 0xfffffffc. bits 1..0 are hardwired to 00b. address offset: 0x010 bit type mod description 31:2 1:0 rw r vid vidbotbase - video bottom field base address. this is the destination starting address for the bottom field. default value is 0xfffffffc. bits 1..0 are hardwired to 00b. address offset: 0x014 bit type mod description 31:18 17:16 rw r vid dispstride - display stride. this register defines the address increment in bytes to be added to the address of the last pixel of a display line, to generate the address of the next consecutive display line. if the address difference between two con- secutive display lines is zero (i.e, they are physically consecutive) than dispstride should be set (by the driver software) to zero (if dispmode=1) or to the display line size in bytes (if dispmode=0). default value is 0xfffc. bits 1..0 are hardwired to 00b. 15:9 r reserved. returns zero. 8rcall vidovf - video fifo overflow flag. this bit is asserted by the video fifo server when an overflow of the video fifo occurs. this bit is cleared when the host tries to write 1 to it. in case of concurrent accesses to this bit, it remains 1. 1 - a vfifo overflow occurred. 0 - no overflow (default value). 7:2 r reserved. returns zero. 1rwall snapshot - frame grab mode. if this bit is asserted the zr36067-lv goes into frame grab mode. when deasserted con- tinuous display of video is resumed. 1 - frame grab mode. 0 - continuous display mode (default value). 0 rs snap framegrab - frame grabbing command/ status. when this bit is asserted by the host and snapshot is asserted, the zr36067-lv will transfer the next two fields (indicated by the vsync signal) to memory. at the end of the second field this bit will be cleared internally, indicating that the frame grabbing has been completed and video transfer has been stopped. in case of concurrent accesses to this bit, the result is 0. 1 - start frame grabbing. 0 - frame grabbing completed (default value). address offset: 0x018 bit type mod description 31 rw all viden - video display enable. if this bit is cleared by the host, video write dma transfers are disabled. when enabled, the video dma controller operates normally. 1 - normal video transfer mode. 0 - video write transfers disabled (default value). 30:24 rw vid minpix - minimum number of doublewords. this parameter defines a threshold value. when the number of doublewords inside the video fifo has reached this value a video- write burst is requested. default value is 0x0f. range 0x01 - 0x3c. the l.s. bit of this field (bit 24) is also used to configure the platform pci bridge type, so the actual resolution of minpix is limited by the triton bit. when the triton bit is 1, only odd values of minpix are supported. when the triton bit is 0, only even values are supported. 24 rw vid triton - pci bridge controller type. this parameter configures the pci req behavior to match the platform pci bridge characteristics. 0 - intel triton bridge controller. the req assertion and de-assertion conditions are modified accordingly. 1 - other pci bridge controllers. default value is 1. this bit is also used as the l.s. bit of minpix. address offset: 0x014 (continued) bit type mod description 29 enhanced pci bus multimedia controller (low-voltage) 13.8 masking map top register this register contains the dword base address of the top masking map. 13.9 masking map bottom register this register contains the dword base address of the bottom masking map. 13.10 overlay control register this register contains the parameters controlling overlay (byte 1) and masking map addressing (byte 0). 23:22 r reserved. returns zero. 21:12 rw vid vidwinht - video window height. this register defines the number of lines that should be displayed by the zr36067-lv. if dispmod = 0, vidwinht is half the number, if dispmod = 1, it is the entire number of display lines. default value is 0x0f0. 11:10 r reserved. returns zero. 9:0 rw vid vidwinwid - video window width. this register defines the width of the video window in number of pixels. default value is 0x3ff. address offset: 0x01c bit type mod description 31:2 1:0 rw r vid masktopbase - masking map top base address. this is the source starting address of the top field for the masking map read transfers. default value is 0xfffffffc. bits 1..0 are hardwired to 00b. address offset: 0x018 (continued) bit type mod description address offset: 0x020 bit type mod description 31:2 1:0 rw r vid maskbotbase - masking map bottom base address. this is the source starting address of the bottom field for the masking map read trans- fers. default value is 0xfffffffc. bits 1..0 are hardwired to 00b. address offset: 0x024 bit type mod description 31:16 r reserved. returns zero. 15 rw vid ovlenable - overlay enable flag. when enabled the masking information in the video mask is evaluated to allow overlay of other windows or graphics. when disabled the video window is always on top. 1 - overlay enabled, 0 - overlay disabled (default value). 14:8 r reserved. returns zero. 7:0 rw vid maskstride . this register defines the address increment in doublewords that is needed to get from the end of a mask line to the beginning of the next. if the address difference between two con- secutive mask lines in main memory is zero (i.e, they are physically consecutive) then maskstride should be set (by the driver soft- ware) to zero (if dispmode=1) or the mask line size in doublewords (if dispmode=0). default value is 0xff. 30 enhanced pci bus multimedia controller (low-voltage) 13.11 system, pci and general purpose pins control register this register contains the software reset bit (byte 3), a pci control parameter (byte 2) and the general purpose pins direc- tion parameter (byte 0). 13.12 general purpose pins and guestbus control register (i) this register contains the values for general purpose outputs (byte 3) and timing parameters for the first four guests (bytes 1-0). 13.13 mpeg code source address register this register contains the dword base address for mpeg mode code dma transfers. address offset: 0x028 bit type mod description 31:25 r reserved. returns zero. 24 rw all softreset - software reset. this bit is asserted by the host to reset the zr36067-lv. if this bit is set to 0 all resetta- ble registers in the device will be reset to their default value, except: - the softreset bit, - the pci interface. the device continues to respond according to the pci specification and can be the target of a pci transfer targeted at the asrs or config. space. the transfer (single- or burst-write) asserting this bit will not be terminated abnor- mally. the device will not initiate any pci transfers during reset, because all dma channels are disabled. this register continues to be programmable. during reset, actually, only this bit of the asrs can be modified by the host (e.g. turning reset off). a power on (hardware) reset also asserts this bit. after the hardware reset is over, a large portion of the zr36067-lv (see above) will remain in reset mode until the softreset bit is deasserted. after this bit is deasserted, all registers retain their default values, all dma channels remain disabled and all asrs are programmable in accordance with their modification condition. 1 - no reset, 0 - reset (default value after power on). 23:19 r reserved. returns zero. 18:16 rw all waitstate - pci wait state control. this parameter defines the number of wait states inserted by the pci slave logic. during each pci transfer cycle to the zr36067-lv, the device will de-assert trdy according to this value. default value 000b. 15:8 r reserved. returns zero. 7:0 rw res genpurdir - general purpose pins direction. these eight bits define the direction of the gpio7..0 pins, respectively. a 1 defines the corresponding pin as an input, a 0 as an output. default value is 0xff (all inputs). address offset: 0x02c bit type mod description 31:24 rw all genpurio - general purpose input/output. the function of this register depends on the setting of genpurdir. for each pin configured as input (default): - reading this bit will return the current value of the input pin. - writing to an input has no meaning, no change of that bit. for each pin configured as output: - reading this bit will return the value on the corresponding output pin. (if there is no external short circuit, this is the last value written by the host.) - writing will change the output to the value specified. default value is 0xf0. 23:16 r reserved. returns zero. 15:14 rw res duration time for guest 3: 00b - tdur3 = 3 pci clocks (default value), 01b - tdur3 = 4 pci clocks, 10b - tdur3 = 12 pci clocks, 11b - tdur3 = 15 pci clocks. 13:12 rw res recovery time for guest 3: 00b - trec3 = 3 pci clocks (default value), 01b - trec3 = 4 pci clocks, 10b - trec3 = 12 pci clocks, 11b - trec3 = 15 pci clocks. 11:8 rw res duration and recovery times for guest 2 (same structure as defined for guest 3 above). 7:4 rw res duration and recovery times for guest 1 (same structure as defined for guest 3 above). 3:0 rw res duration and recovery times for guest 0 (same structure as defined for guest 3 above). address offset: 0x030 bit type mod description 31:2 1:0 rw r cod codmembase - mpeg code memory base address. this is the source starting address for the code-read dma transfers. default value is 0xfffffffc. bits 1..0 are hardwired to 00b. 31 enhanced pci bus multimedia controller (low-voltage) 13.14 mpeg code transfer control register this register contains status and control bits and configuration parameters for code dma transfers. address offset: 0x034 bit type mod description 31 r reserved. returns zero. 30 rc all codtime - mpeg code-write timeout flag. this bit is set to 1 by the guestbus master if a code-write cycle on the guestbus lasts more than 64 pci clocks. this might happen when the accessed guest holds gws low too long. it is cleared (0) by the host writing a 1. priority is given to the guestbus master in case of concurrent accesses to this bit. 1 - a code-write cycle has timed out. 0 - no timeout occurred (default value). 29 r cempty - code fifo empty. this bit reflects the status of the internal code buffer. when the buffer is empty this bit shows one, otherwise zero. 1 - buffer is empty (default value), 0 - buffer is not empty. 28 rw cod cflush - code fifo flush. this bit is used by the host to reset the internal code buffer. when it is asserted remaining code in the buffer is lost. after it is deasserted the buffer is empty and ready to receive data. 1 - flush internal code buffer (default value), 0 - normal operation of buffer. 27:23 r reserved. returns zero. 22:20 rw cod codguestid - code guest identification. these three bits select the guest to be accessed for mpeg code dma transfers. default after reset is 000b. 19 r reserved. returns zero. 18:16 rw cod codguestreg - mpeg code guest regis- ter. register indication of accessed guest for mpeg code dma transfers. within each guest up to eight registers can be addressed. default after reset is 000b. 15 r unused. returns zero. 14:12 rw cod codmemsize - mpeg code memory buffer size. this value determines the size of the contiguous memory buffer allocated by the host for storage of mpeg compressed data: 000b - 8 kbyte, 001b - 16 kbyte, 010b - 32 kbyte, 011b - 64 kbyte (default value), 100b - 128 kbyte, 101b - 256 kbyte. 110b - 111b will result in the default value. 11 r reserved. returns zero. 10:8 rw cod codmemstep - mpeg code memory report step. in mpeg mode, this value determines the amount of code data, in quanta of 8 kbytes, after which the zr36067-lv notifies its position (within the buffer) to the host, by requesting an interrupt. for proper operation, the buffer size must be greater than or equal to the report step size: 000b - irq every 8 kbytes, 001b - irq every 16 kbytes (default value), 010b - irq every 32 kbytes, 011b - irq every 64 kbytes, 100b - irq every 128 kbytes, 101b - irq every 256 kbytes. 110b - 111b will result in the default value. 7rwall codreaden - mpeg code-read enable. in mpeg mode, if this bit is cleared by the host, the code-read transfers are stopped. the current code-read pointer retains its value. when this bit is set to 1, the zr36067-lv resumes code-read transfers. default value is 0. 6:4 r reserved. returns zero. 3:1 rw cod codtrshld - mpeg internal code fifo threshold. in mpeg mode, if the fullness of the fifo drops below this threshold value (in doublewords) and codreaden is set to 1, a code-read burst is requested. default value is 0x6. 0rwcod codautoen - mpeg code-read auto re- initialize enable. in mpeg mode, if this bit is cleared, every time the code memory pointer reaches the end of the allocated space (i.e. codmembase plus codmemsize) the code-read transfer is stopped. if the bit is set the code memory pointer is reinitialized at the end of the allocated space and code-read transfers run in a cyclic manner. default value is 0. address offset: 0x034 (continued) bit type mod description 32 enhanced pci bus multimedia controller (low-voltage) 13.15 mpeg code memory pointer register this register contains the pointer to the code memory of the host in mpeg mode. 13.16 interrupt status register this register contains the status of the interrupt sources. 13.17 interrupt control register this register contains the control byte for the interrupt handling. address offset: 0x038 bit type mod description 31:16 r unused. returns zero. 15:0 rw cod codmempoint - mpeg code memory pointer. in mpeg mode, this register reflects the current position of the code memory pointer within the range of the allocated host memory. the value represents the number of doublewords from the base address. writing to this register by the host can be used for reset or moving the pointer inside the code memory space, only if codreaden is deasserted. a value pointing outside the memory size should not be used. default value is zero. address offset: 0x03c bit type mod description 31 r reserved. returns zero. 30 rc all girq1 - girq1 input pin. a 1 indicates that a guest requested an interrupt on the girq1 input pin. this bit is cleared when the host tries to write 1 to it. in case of concurrent accesses to this bit, it remains 1. default value is 0 (no irq). 29 rc all girq0 - girq0 input pin. a 1 indicates that a guest requested an interrupt on the girq0 input pin. this bit is cleared when the host tries to write 1 to it. in case of concurrent accesses to this bit, it remains 1. default value is 0 (no irq). 28 rc all codrepirq - mpeg code report step interrupt request. a 1 indicates that the code memory buffer pointer, in mpeg mode, has passed a report step. this bit is cleared when the host tries to write 1 to it. in case of concurrent accesses to this bit, it remains 1. default value is 0 (no irq). 27 rc all jpegrepirq - jpeg report interrupt request. a 1 indicates that a jpeg field/ frame process has ended. in compression modes, a field compression has ended and its data has been transferred to the allocated code buffer in system memory. in decompression modes, a field/frame decompression has ended and its corre- sponding code buffer can be re-loaded by the software. this bit is cleared when the host tries to write 1 to it. in case of concurrent accesses to this bit, it remains 1. default value is 0 (no irq). 26:0 r reserved. returns zero. address offset: 0x040 bit type mod description 31 r reserved for future interrupt source. returns 0. 30 rw all girq1en - girq1 enable. when enabled and intpinen is set to 1, each positive edge of the girq1 input will generate an interrupt request on the pci bus inta output pin. when cleared, girq1 continues to reflect the corresponding interrupt pin. 1 - girq1 enabled, 0 - girq1 disabled (default value). 29 rw all girq0en - girq0 enable. when enabled and intpinen is set to 1, each positive edge of the girq0 input will generate an interrupt request on the pci bus inta output pin. when cleared, girq0 continues to reflect the corresponding interrupt pin. 1 - girq0 enabled, 0 - girq0 disabled (default value). 28 rw all codrepirqen - mpeg mode code report step interrupt enable. when enabled and intpinen is set to 1, an interrupt request will be generated on the pci bus inta output pin each time the code memory buffer pointer passes a report step. when codrepirqen is cleared, codrepirq continues to reflect the internal report step interrupt request. 1 - interrupt request enabled, 0 - disabled (default value). address offset: 0x03c (continued) bit type mod description 33 enhanced pci bus multimedia controller (low-voltage) 13.18 i 2 c-bus register this register contains the control bits of the i 2 c bus. 13.19 postoffice register this register contains the status (byte 3), control (byte 2) and data (byte 0) parameters for postoffice transfers. 27 rw all jpegrepirqen - jpeg report interrupt request enable. when enabled and intpinen is set to 1, an interrupt request will be gener- ated on the pci bus inta output pin after the end of each jpeg field/frame process. when jpegrepirqen is cleared, jpe- grepirq continues to reflect the jpeg process status. 1 - interrupt request enabled, 0 - disabled (default value). 26:25 r reserved. returns zero. 24 rw all intpinen - inta pin enable. when cleared, none of the events that may cause an inter- rupt request on the pci bus inta pin is enabled. nevertheless the interrupt status register continues to reflect all interrupt input pins and internal interrupt requests. 1 - every interrupt request is passed onto the pci bus, 0 - inta disabled (default value). 23:0 r reserved. returns zero. address offset: 0x044 bit type mod description 31:2 r unused. returns zero. 1rwall sda - i 2 c sda line. when the host writes 0 to this bit, the sda output signal goes low. when the host writes 1, sda goes into tri- state. when the host reads this bit it reflects the current level on the sda pin. default value is 1. 0rwall scl - i 2 c scl line. when the host writes 0 to this bit, the scl output signal goes low. when the host writes 1, scl goes into tri- state. when the host reads this bit it reflects the current level on the scl pin. default value is 1. address offset: 0x040 (continued) bit type mod description address offset: 0x200 - 0x2ff bit type mod description 31:26 r reserved. returns zero. 25 r all popen - postoffice request pending flag. this bit is set internally to 1 when the host writes to the postoffice data byte. it is cleared when a postoffice cycle is com- pleted or a postoffice time-out occurred. in case of concurrent accesses to this bit, the result is 0. 1 - postoffice request is pending. 0 - postoffice request is not pending (default value). 24 rc all potime - postoffice time-out flag. this bit is set to 1 by the guestbus master if a postof- fice cycle on the guestbus lasts more than 64 pci clocks. this might happen when the accessed guest holds gws low for too long. it is cleared (0) by the host writing a 1. in case of concurrent accesses to this bit, it remains 1. 1 - postoffice cycle has timed out. 0 - no time-out occurred (default value). 23 rw all podir - postoffice direction flag. this bit defines the direction of the postoffice opera- tion: 0 - read (host reads guest). 1 - write (host writes to guest). default after reset is 1. 22: 20 rw all poguestid - postoffice guest identification. these three bits select the guest to be accessed. they determine which of the gcs pins will be asserted in the requested postof- fice cycle. up to eight guests can be identified. default after reset is 000b. 19 r reserved. returns zero. 18:16 rw all poguestreg - postoffice guest register. register indication of accessed guest. within each guest up to eight registers can be addressed. the poguestreg bits determine the register address that will be presented on the gadr2:0 lines in the requested postof- fice cycle. default after reset is 000b. 15:8 r reserved. returns zero. 7:0 r, w all podata - postoffice data. an eight-bit register containing the data being transferred during postoffice reads and writes. default after reset is 00000000b. 34 enhanced pci bus multimedia controller (low-voltage) 13.20 jpeg mode and control this register contains the jpeg mode configuration and optional control bits. 13.21 jpeg process control this register contains the jpeg process control. address offset: 0x100 bit type mod description 31 rw all jpg - jpeg/mpeg mode selection. this bit selects between the two code dma controller modes. 1 - jpeg mode. 0 - mpeg mode. default value is 0 30 : 29 rw jpg jpgmode - jpeg sub-modes selection. these two bits configure the jpeg sub- mode. 11b - motion video compression. 10b - motion video decompression. 01b - still image compression. 00b - still image decompression. default value is 11b 28 : 7 r reserved. returns zero. 6 rw jpg rtbsy_fb - rtbsy feed-back. enables the zr36067-lv to de-assert the pxen signal if rtbsy is detected in the active area of the field. 1 - enable pxen de-assertion if rtbsy is detected. allowed only if syncmstr=1. 0 - disable pxen de-assertion. default value is 0 5rw go_en - the enable bit of the zr36060 start or zr36050 go command cycle. the bit, when 1, enables the guestbus master to perform a jpeg start or go cycle. during a jpeg go cycle the zr36067-lv assumes that the correct address (0x00h) is pre- latched in an external address register. it is the hosts responsibility to perform the write operation to load the address. the host must de-assert go_en whenever it accesses the zr36050 (using postoffice) in a middle of a jpeg process, or changes the address latched in the external register. the host must also de-assert go_en before postoffice pseudo write-through burst cycles. in this case, the host also has to wait at least 0.5 microseconds before initiating the burst (to allow the jpeg start or go cycle to com- plete, if one was started). default value is 0 (not enabled). 4 rw jpg syncmstr - sync signals master. this bit configures the zr36067-lv as a sync master. this configuration is allowed in all jpeg modes except motion video compression 1 - the zr36067-lv is the sync signal master. 0 - the sync signals are driven from an external video source. default value is 0 3 rw jpg fld_per_buff - number of fields per code buffer. this bit reflects the system memory code buffer structure, in jpeg compression and decompression modes. 1 - the code buffer contains one code field. 0 - the code buffer contains two consecutive code fields, one code frame. default value is 0 2 rw jpg vfifo_fb - vfifo feed-back. enables the zr36067-lv to de-assert the pxen signal according to the status of the video fifo. 1 - enable pxen de-assertion if the pixel buffer is close to overflow. allowed only if syncmstr=1. 0 - disable pxen de-assertion if the pixel buffer is close to overflow. default value is 0 1 rw jpg cfifo_fb - cfifo feed-back. enables the zr36067-lv to de-assert the pxen signal according to the status of the code fifo. 1 - enable pxen de-assertion if the code buffer is close to overflow/underflow. allowed only if syncmstr=1. 0 - disable pxen de-assertion if the code buffer is close to overflow/underflow. default value is 0 0 rw jpg still_litendian - still image pixel little endian format selector. this control bit defines the pixel format in still image com- pression and decompression. 1 - the pixel format is little endian. 0 - the pixel format is gib endian. default value is 1. address offset: 0x104 bit type mod description 31: 8 r reserved. returns zero. 7rwall p_reset - process reset. this bit is asserted by the host in order to reset the zr36067-lv jpeg-related state machines. the bit must be asserted at the beginning of a jpeg process. while it is asserted, all of the jpeg process parameters may be configured by the host. 1 - no reset. 0 - reset. default value is 1. 6 r reserved, returns zero. 5rw codtrnsen - jpeg code transfer enable. this bit enables the code transfer between the internal code buffer and the system memory in all of the jpeg modes. 1 - code transfer is enabled. 0 - code transfer is disabled. default value is 0. address offset: 0x100 (continued) bit type mod description 35 enhanced pci bus multimedia controller (low-voltage) 13.22 vertical sync parameters this register contains the vsync parameters to be generated by the zr36067-lv as a sync master. 13.23 horizontal sync parameters this register contains the hsync parameters to be generated by the zr36067-lv as a sync master. 13.24 field horizontal active portion this register contains the horizontal parameters of the active portion of the processed field. 13.25 field vertical active portion this register contains the vertical parameters of the active portion of the processed field. 13.26 field process parameters this register contains the general parameters of the field process. 13.27 jpeg code base address this register specifies the base address of the code buffer table. 13.28 jpeg code fifo threshold this register specifies code fifo threshold in jpeg mode. 4 : 1 r reserved, returns zero. 0rwall active - this command bit is asserted by the host in order to initiate a jpeg process. 1 - active is asserted. 0 - active is deasserted. default value is 0. address offset: 0x108 bit type mod description 31: 24 rw reserved. returns zero. 23: 16 rw jpg vsyncsize - vsync signal length. the vsync length is measured in lines. default value is 0x06. 15 : 0 rw jpg frmtot - frame total size. the total number of lines per frame. this parameter must be an odd number. default value is 0x020d (525, for ntsc) address offset: 0x10c bit type mod description 31 : 16 rw jpg hsyncstart - hsync signal start point. the point in the line (measured in number of vclks) at which hsync should be asserted. default value is 0x0280 (640, for square pixel ntsc). 15 : 0 rw jpg linetot - line total size. the total number vclks in a line. default value is 0x030c (780, for square pixel ntsc) address offset: 0x110 bit type mod description 31 : 16 rw jpg nax - the first pixel in a line to be processed. counted from the active edge of hsync. default value is 0x0000. 15 : 0 rw jpg pax - the number of pixels to be processed in a line. default value is 0x0280 (640, for square pixel ntsc) address offset: 0x104 (continued) bit type mod description address offset: 0x114 bit type mod description 31 : 16 rw jpg nay - the first line in a field to be processed. counted from the active edge of vsync. default value is 0x000a. 15 : 0 rw jpg pay - the number of lines to be processed in a field. default value is 0x00f0 (240, for ntsc) address offset: 0x118 bit type mod description 31 : 1 r reserved. returns zero. 0 rw jpg odd_even - first field type. the type of the first field to be processed. odd type is defined as the field in which the active edge of vsync is asserted during the active portion of the horizontal line. even type is defined as the field in which the active edge of vsync is asserted during the active portion of hsync. 1 - the first field is odd. 0 - the first field is even. default value is 1. address offset: 0x11c bit type mod description 31 : 0 rw jpg i_stat_com_ptr - the memory address of the code buffer table. default value 0xfffffffc. address offset: 0x120 bit type mod description 31 : 8 r reserved, returns zero. 7 : 0 rw jpg jpegcodtrshld - jpeg code fifo thresh- old. in compression, if the fullness level of the code fifo (in doublewords) goes above this threshold the pci bus is requested. in decompression, if the fullness level of the code fifo (in doublewords) goes under this threshold the pci bus is requested. default value is 0x50h 36 enhanced pci bus multimedia controller (low-voltage) 13.29 jpeg codec guest id this register contains the zr36060 (or zr36050) guest id for the jpeg start (or go command) cycle. 13.30 guestbus control register (ii) this register contains the timing parameters of an additional 4 guests (the first 4 guests parameters are defined in 13.12 general purpose pins and guestbus control register (i)). 13.31 still transfer register this register is used for data and control in still image compres- sion or decompression. address offset: 0x124 bit type mod description 31 :7 r reserved, returns zero. 6 : 4 rw jpg jpeguestid - jpeg codec guest id. these three bits define the guest port to which the zr36060 (or zr36050) is connect- ed, in order to perform the jpeg start (or go command) cycle. default value is 100b 3 r reserved, returns zero. 2 : 0 rw jpg jpeguestreg - jpeg codec register. these three bits define the guest register for the jpeg go command to a zr36050. not used with zr36060. default value is 000b address offset: 0x12c bit type mod description 31 : 16 r reserved, returns zero. 15 : 14 rw res duration time for guest 7: 00b - tdur 7 = 3 pci clocks (default value), 01b - tdur7 = 4 pci clocks, 10b - tdur7 = 12 pci clocks, 11b - tdur7 = 15 pci clocks. 13 :12 rw res recovery time for guest 7: 00b - trec7 = 3 pci clocks (default value), 01b - trec7 = 4 pci clocks, 10b - trec7 = 12 pci clocks, 11b - trec7 = 15 pci clocks. 11 : 8 rw res duration and recovery time of guest 6 (same structure as defined for guest 7 above) 7 : 4 rw res duration and recovery time of guest 5 (same structure as defined for guest 7 above) 3 : 0 rw res duration and recovery time of guest 4 (same structure as defined for guest 7 above) address offset: 0x300 bit type mod description 31/7 r all still_bsy - still transfer busy indication bit. the bit indicates to the host whether the still transfer register is available to write the next pixel in still image compression mode. when this bit is 0, the register is available. the bit location depends on the still_litendian configuration bit in the jpeg mode and control register. if little endian format was selected then the bit location is 31. if gib endian format was selected then the bit location is 7. when still image compression mode is selected (and after p_reset was de-assert- ed), the bit is 0. after the host writes a pixel, the bit is set to 1. the bit remains 1 until the pixel is synchronized to the video clock and going to be driven out from the zr36067-lv video port. then when the register is avail- able again, the bit is reset to 0. when still image decompression mode is selected (and after p_reset was de-assert- ed), the bit is 1. after the zr36067-lv fetches a new pixel, and the pixel is ready for the host to read it, the bit is reset to 0. it is set to 1 again after the pixel was read. 1 - the register is not available. 0 - the register is available. default value is 0. 31 : 0 rw all still transfer pixel register. the byte order (rgb or bgr) is defined by the still_litendian configuration bit in the jpeg mode and control register. if little endian format was selected, the byte order is: r7..0 on bits 23..16. g7..0 on bits 15..8. b7..0 on bits7..0. if gib endian format was selected, the byte order is: r7..0 on bits 15..8. g7..0 on bits 23..16. b7..0 on bits 31..24. 37 enhanced pci bus multimedia controller (low-voltage) 14.0 electrical characteristics absolute maximum ratings storage temperature .........................................65c to +150c supply voltage v ddio ........................................-0.5 v to +6.0 v supply voltage v ddc .........................................-0.5 v to +4.0 v dc output voltage ..................................... 0.5 v to v ddio + 0.5 dc input voltage....................................... -0.5 v to v ddio + 0.5 dc output current .....................................-100 ma to +100 ma dc input current........................................ -100 ma to +100 ma max power dissipation......................................1.6w @ 33 mhz note: stresses above these values may cause permanent device failure. functionality at or above those limits is not implied. exposure to absolute maximum ratings for extended periods may affect device reliability. operating range temperature. ..........................................................0c to +70c v ddio ............................................................... 4.75 v to 5.25 v v ddc ................................................................ 3.13 v to 3.47 v dc characteristics table 15: digital inputs symbol parameter min max unit test conditions v il input low voltage 0.8 v v ih input high voltage 2.0 v v iil input low voltage (sda, scl) 0.3 x v ddio v v iih input high voltage (sda, scl) 0.7 x v ddio v i li input leakage current 10 [1] m a c in input capacitance 8 pf 1. input pullup leakage current for sda is -200 m a. table 16: digital outputs symbol parameter min max unit test conditions v ol output low voltage 0.4 v v oh output high voltage 3.8 v i lo output leakage current 10 m a c out output capacitance 8 pf table 17: pci bus symbol parameter min max unit test conditions v il input low voltage 0.8 v v ih input high voltage 2.0 v v ol output low voltage 0.55 v v oh output high voltage 2.4 v i lih input leakage current 70 m av in = 2.7/0.5 v c pciclk pciclk input capacitance 5 12 pf 38 enhanced pci bus multimedia controller (low-voltage) table 18: power supply current consumption symbol parameter min max unit test conditions i ddc power supply current, 3.3v supply 170 ma f vclkx2 = 29.5mhz v ddc = 3.47v v ddio = 5.25v i ddio power supply current, 5.0v supply 100 ma f vclkx2 = 29.5mhz v ddc = 3.47v v ddio = 5.25v 39 enhanced pci bus multimedia controller (low-voltage) 15.0 ac timing specifications 15.1 pci bus timing table 19: pci bus timing symbol parameter min max unit t pci pciclk period 30 ns t ph pciclk high 12 ns t pl pciclk low 12 ns t a3 pciclk slew rate 1 4 v/ns t a4 pciclk to signal valid delay - bussed signals 2 11 ns t a5 pciclk to signal valid delay - point-to-point 2 12 ns t a6 float to active delay 2 11 ns t a7 active to float delay 28 ns t a8 input setup time to pciclk - bussed signals 7 ns t a9 input setup time to pciclk - point-to-point 10 ns t a10 input hold time from pciclk 0 ns t a11 unloaded output rise/fall time 1 5 v/ns between 0.4 v and 2.4 v pciclk figure 10. pci bus timing output delay 3-state output t pci t ph t a3 t pl t a4 t a5 t a6 t a7 input t a9 t a8 t a10 t a11 40 enhanced pci bus multimedia controller (low-voltage) 15.2 video bus timing table 20: video bus timing symbol parameter min max unit t v2p vclkx2 period 31 45 ns 40% to 60% duty cycle t v2t vclkx2 rise/fall transition 5 ns t vt vclk rise/fall transition 5 ns t vis video bus input setup 11 ns t vih video bus input hold 0 ns t vclkh vclk hold -2 ns vclkx2 figure 11. video bus timing vclk inputs t v2p t vis t vclkh t vis t vih t v2t t v2t table 21: video bus outputs symbol parameter min max unit t vbo video bus output delay 1 16 ns typical output load 50pf t vbh video bus output hold (all signals except pxen )1 ns t vpo pxen output delay 17 ns t vph pxen output hold 2 ns vclkx2 figure 12. video bus timing C control and data output signals vclk video output t vpo pxen t vbo t vbh t vph (incl sync) 41 enhanced pci bus multimedia controller (low-voltage) 15.3 guestbus timing table 22: guestbus interface timing symbol parameter min max unit t carw gcs n / gadr2..0 setup 16 ns t rwca gcs n / gadr2..0 hold 16 ns t rwdur gwr / grd low 90 ns determined by parameter t dur and signal gws t rwrec gwr / grd high 90 ns determined by parameter t rec t pd propagation delay, pciclk to output signal 1 16 ns typical output load 70 pf t gdh write data hold, gwr / grd to data float t pci - 16 t pci + 16 ns typical output load 70 pf t grs read data setup 11 ns t grh read data hold 0 ns t girq girq1..0 high / low 2 * t pci ns t gws wait state setup, gws delay after gwr /grd (t dur -1) * t pcp - t pd - t grs ns t gwl wait state low [1] t pci ns t gwh wait state hold, gws to gwr /grd t pcp + t pd + t grs ns 1. for each period of t pci the duration of the transfer will be extended for one pci clock period. gcs n pciclk gadr[2:0] gwr 1 2 3 4 5 6 7 8 9 10 11 12 13 t car t rwc t rwdur grd t car t rwc t rwdu t rwrec gws gdat[7:0] t pd t gdh data valid from zr36067-lv data valid from guest n t grs t grh figure 13. guestbus timing grd /gwr gws t rwdur t gwl t gwh t gws wait-state timing 42 enhanced pci bus multimedia controller (low-voltage) 15.4 codec bus interface timing table 23: codec bus interface timing symbol parameter min max unit t ccs ccs setup 10 ns t cch ccs hold 0 ns t cpd code output propagation delay 3 9 ns typical load 15pf t chd code output hold delay 1 ns t cis code input setup 9 ns t cih code input hold 0 ns t cbo cbusy output propagation delay 2 16 ns typical load 15pf t cbh cbusy output hold delay 2 ns t ces cend setup 9 ns t ceh cend hold 1 ns code[7:0] figure 14. codec interface timing ccs cbusy cend vclkx2 t cbo data valid from codec t cis t cih t cpd t ccs t cc t ces t cbh t ceh t chd t ccs 43 enhanced pci bus multimedia controller (low-voltage) 16.0 mechanical data 16.1 pinout pin no. pin name pin no. pin name pin no. pin name pin no. pin name pin no. pin name pin no. pin name pin no. pin name pin no. pin name 1 vss 27 devsel 53 vss 79 girq0 105 vss 131 code6 157 b5 183 test 2 vddc 28 vss 54 vddc 80 girq1 106 vddc 132 vddio 158 b6 184 inta 3vss 29stop 55 ad6 81 vddio 107 gdat3 133 code7 159 b7 185 vddio 4 idsel 30 par 56 ad5 82 gcs0 108 vss 134 cbusy 160 vddio 186 pcirst 5 ad23 31vss 57vss 83gcs1 109 gdat4 135 vss 161 uv0 187 pciclk 6 vss 32 c/be1 58 ad4 84 gcs2 110 gdat5 136 ccs 162 vss 188 gnt 7 ad22 33 vddio 59 ad3 85 gcs3 111 vss 137 vss 163 uv1 189 vss 8 ad21 34 ad15 60 vss 86 gcs4 112 gdat6 138 vclk 164 uv2 190 req 9 vss 35 vss 61 ad2 87 vss 113 gdat7 139 vddio 165 vss 191 ad31 10 ad20 36 ad14 62 ad1 88 vss 114 vddio 140 start 166 uv3 192 vddio 11 ad19 37 vss 63 vss 89 vddio 115 gws 141 rtbsy 167 uv4 193 vss 12 vddio 38 ad13 64 ad0 90 gcs5 116 grdy 142 pxen 168 uv5 194 ad30 13 vss 39 ad12 65 vddio 91 gcs6 117 gwr 143 fi 169 uv6 195 ad29 14 ad18 40 vss 66 scl 92 gcs7 118 grd 144 vddio 170 uv7 196 vss 15 ad17 41 ad11 67 sda 93 vss 119 vddio 145 vsync 171 vss 197 ad28 16 vss 42 c/be0 68 vss 94 vddio 120 vss 146 hsync 172 vddio 198 ad27 17 ad16 43 vss 69 vddio 95 gadr0 121 cend 147 vss 173 y0 199 vss 18 vddio 44 vddio 70 gpio0 96 gadr1 122 code0 148 b0 174 y1 200 ad26 19 c/be2 45 ad10 71 gpio1 97 vddc 123 code1 149 b1 175 y2 201 ad25 20 vss 46 ad9 72 gpio2 98 gadr2 124 code2 150 b2 176 y3 202 vss 21 frame 47 vss 73 gpio3 99 gdat0 125 code3 151 b3 177 y4 203 ad24 22 irdy 48 ad8 74 gpio4 100 gdat1 126 vss 152 b4 178 y5 204 c/be3 23 vddio 49 ad7 75 gpio5 101 gdat2 127 vclkx2 153 vss 179 y6 205 vss 24 vss 50 vss 76 gpio6 102 vss 128 vss 154 vddio 180 vss 206 vddio 25 trdy 51 vddio 77 gpio7 103 vss 129 code4 155 vddc 181 y7 207 vddc 26 vss 52 vddc 78 vss 104 vddio 130 code5 156 vss 182 enid 208 vss 44 enhanced pci bus multimedia controller (low-voltage) vss vddc vss idsel ad23 vss ad22 ad21 vss ad20 ad19 vddio vss ad18 ad17 vss ad16 vddio c/be2 vss frame irdy vddio vss trdy vss devsel vss stop par vss c/be1 vddio ad15 vss vss ad13 ad12 ad14 vss 52 1 208 157 53 104 105 156 ZR36067PQC-LV (top view) ad11 c/be0 vss vddio ad10 ad9 vss ad8 ad7 vss vddio vddc vddio vss vss gdat2 gdat1 gdat0 gadr2 vddc gadr1 gadr0 vddio vss gcs7 gcs6 gcs5 vddio vss vss gcs4 gcs3 gcs2 gcs1 gcs0 vddio girq1 girq0 vss gpio7 gpio6 gpio5 gpio4 gpio3 gpio2 gpio1 gpio0 vss sda scl vddio vddio ad0 vss ad1 ad2 vss ad3 ad4 vss ad5 ad6 vddc vss vss vddc vss vss code4 code6 cbusy vss vss vddc vss b5 b6 b7 vddio uv0 vss uv1 uv2 vss uv3 uv4 uv5 uv6 uv7 vss vddio y0 y1 y2 y3 y4 y5 y6 vss y7 enid test inta vddio pcirst pciclk gnt vss req ad31 vss ad30 ad29 vss vddio ad28 ad27 vss ad26 ad25 vss c/be3 vss vddio vddc ad24 vss gdat3 vddio gdat4 b4 gdat5 b3 vss b2 gdat6 b1 gdat7 b0 vddio vss gws hsync grdy vsync gwr vddio grd fi vddio pxen vss rtbsy cend start code0 vddio code1 vclk code2 vss code3 ccs vss vclkx2 code7 vddio code5 45 enhanced pci bus multimedia controller (low-voltage) 16.2 dimensions 46 enhanced pci bus multimedia controller (low-voltage) appendix a: zr36110 - zr36067-lv interface figure 15 describes a recommended interconnection between the zr36067-lv and the zr36100 / zr36110 host bus. zr36110 reset any of the software controlled gpi/o pins (configured as output) of the zr36067-lv may be used as a reset input of the decoder. the software then directly manipulates the reset signal through the corresponding register bit. since the default configuration of the gpio pins after reset is input, a pull down resistor should be applied to the zr36110 reset input. mapping the zr36110 on the zr36067-lvs guestbus the driver software must map the zr36110 on the guestbus: the zr36110s guest id number (0,1,2, or 3) must be configured as a code-write target. the proper timing parameters (tdur = 3, to ensure 82ns, trec = 4, to ensure 100ns) of the zr36110 must be loaded to the guestbus control register (address 0x030). the zr36110 occupies only four 8-bit registers out of the eight reg- isters dedicated to each guest. zr36110 initialization the initialization consists of loading the zr36110 microcodes and parameters. this is done using the postoffice mechanism. the host interface of the zr36110 must be set to 8 bit, intel format, i/o only. the bsln parameter should be set to 2 or 4, for efficient operation. on-line commands and status on-line command writes and status reads are also done using the postoffice mechanism. bitstream transfer some preparations must be done prior to triggering the zr36110 with a go command. the host must allocate a contiguous code buffer in the system memory. bitstream retrieved from the mpeg source is stored in this buffer. the zr36067-lv reads data from this buffer in a dma fashion and transfers it, through the cfifo, to the mpeg decoder. there are several possible sizes of the memory buffer. the host must inform the zr36067-lv of the buffer address, size and report step. after the code buffer in memory is allocat- ed, reported to the zr36067-lv, and filled up for the first time, a zr36110 go command can be issued. immediately after this, the dma code-read cycles must be enabled by setting the dma code-read enable bit to 1. the zr36067-lv then starts fetching data from the main memory buffer using cyclic address- ing. whenever it passes a report step it initializes an interrupt request. within the interrupt service routine the host should check the current position of the zr36067-lv code memory buffer pointer, and decide weather it should refresh an old portion of the buffer with new data from the mpeg source. once the coded data arrives at the cfifo, the gbm unit starts writing it over the guestbus to the zr36110. figure 15. zr36067-lv - zr36100/110 basic interconnection dreq dack buscs buswr busrd busadd[1:0] gcs n gwr grd gadr[2:0] gdat[7:0] grdy zr36100/110 zr36067-lv busdat[7:0] ready idle reset vsync girq0 gpio0 girq1 (optional) (optional) v dd other guests 47 enhanced pci bus multimedia controller (low-voltage) appendix b: md207/md208 - zr36067-lv interface this appendix suggests the basic interconnection between the zr36067-lv and the md207/208 video encoder. naturally, when these two devices are connected together there must be a third device, mastering the yuv bus. figure describes a basic interconnection between the zr36067-lv and the md207/208, with an arbitrary yuv source. this minimum example does not use the graphics overlay capability of the md207/208 md207/208 reset software controlled usage of the reset input of the md207/208 is optional. generally, it is more efficient to connect it to the power-up reset of the circuit, and control the device through the software reset register bit of the md207/208. if a hardware reset is needed in the design, any of the software controlled gpi/o pins (configured as output) of the zr36067-lv may be used as a reset signal. the software then directly manipulates the reset signal through the corresponding register bit of the zr36067-lv. since the default configuration of the gpi/o pins after reset is input, a pull down resistor should be applied to the md207/208 reset input. mapping the md207/208 on the zr36067- lv s guestbus the software driver must map the md207/208 on the guestbus. the proper timing parameters (t dur = 12, t rec = 15) of the md207/ 208 must be loaded to the guestbus control register. reading/writing one byte from/to the md207/208 requires two guestbus cycles: in the first cycle the address (index) of the internal md207/208 register is written, in the second one the data byte is read/written. the rs (register select) input of the md207/208 is used to distinguish between the two types of cycles. connecting this pin to the zr36067-lvs gadr0 virtual- ly creates two md207/208 registers at the level of the guestbus: when gadr0 is low (even registers), the md207/208 expects address to be transferred on its d7:0 bus, when gadr0 is high (odd registers) data is output or input on these lines. another way is to connect gadr2 to rs. sync polarity since, unlike the zr36067-lv, the sync polarity of the md207/ 208 is not programmable, then, depending on the yuv 4:2:2 source, it might be necessary to invert the hsync and vsync of the md207/208. vertical interpolation with the md208 pin 8 is the only one that is different between the md207a and the md208. while in the md207a it is a test pin, normally con- nected to ground, the md208 uses this input to switch its internal vertical interpolation mechanism on and off. when this mecha- nism is on, one field out of every pair is vertically interpolated and the interpolated lines are the ones sent out. since this oper- ation is not always desired (e.g., in high resolution still pictures of videocd 2.0) it must be controlled by the software. the natural way to obtain this control is using one of the gpi/os. it is better to pull this pin down in order for the same layout to support both the md207a and the md208. figure 16. zr36067-lv - md207/208 basic interconnection cs gcs n gwr grd gadr[0] gdat[7:0] vclkx2 md207a/208 zr36067-lv vclk gpi/on hsync v dd other guests rs rd wr d[7:0] reset vclk hsync vsync blank yd[7:0] cd[7:0] test/fldintr vsync y[7:0] u/v[7:0] gpi/on (optional) (optional) (optional) yuv 4:2:2 source 48 enhanced pci bus multimedia controller (low-voltage) appendix c: fitting the input size to the required display window the zr36067-lv can crop the input video and scale it down to match any display size required by different applications, as long as the required size is not larger than the original input. this appendix provides some programming guidelines for proper setting of the zr36067-lv parameters involved in this process. for better understanding, a typical example is detailed along with the general explanations. it is assumed that the driver software knows the following basic parameters about the incoming video: it is assumed that ha is an even number. it is also assumed that from knowing the video input format, the driver knows how to set the following zr36067-lv parameters, such that the entire active portion of the video input would have been sampled: the following equation connects hstart, hend, and wa: wa = hend - hstart + 1 in the example, hend = 841, hstart = 122. the following equation connects vstart, vend, and ha: ha/2 = vend - vstart + 1 in the example, vend = 249, vstart = 10. the driver receives from the application software the parameters that define the size of the rectangle, on the monitor, that should be filled with video pixels. this is referred to as the destination rectangle: obviously, in many cases the size of the video rectangle to be displayed is different (smaller) than the size of the active video input sampled by the zr36067-lv. in the example: vidwinwid = 597, vidwinht = 199. (assuming dispmod = 0, this means that the target video window in the example is 597x398). in such cases, out of the parameters above, the driver software must determine the following zr36067-lv parameters, such that the quality of the displayed video is optimal in the sense that the decimation factors will be as small as possible and the portions of the input that are cut out (cropped) will also be as small as possible. wt total width of the input field (i.e., in ccir ntsc wt = 858). wa active width of the input field (i.e., in ccir ntsc wa = 720). ht total height of the input frame (i.e., in ccir ntsc ht = 525). ha active height of the input frame (i.e., in ccir ntsc ht = 480). hspol the polarity of hsync, as defined in the zr36067-lv data sheet. vspol the polarity of vsync, as defined in the zr36067-lv data sheet. hstart the number of pixels, from the active edge of hsync, after which the zr36067-lv starts to sample the input. hend the number of pixels, from the active edge of hsync, after which the zr36067-lv stops sampling the input. vstart the number of lines, from the active edge of vsync, after which the zr36067-lv starts to sample the input. vend the number of lines, from the active edge of vsync, after which the zr36067-lv stops sampling the input. vidwinwid width of the video rectangle. vidwinht if dispmode=1 (single field display) this is the height of the video rectangle. if dispmode=0 (emulation of inter- laced video) this is half of the height of the video rectangle (i.e., the height of one destination field). note that if dispmode=0 the vertical size of the video rectangle must be an even number. this limitation might conflict with applications that will require a video window of a specific, odd vertical size. such conflicts will be resolved by the driver software, which in this case will build a rectangle one line shorter than required, and then fill-in the missing line (a-priori) with a background color. hcrop1 the number of pixels, that will be dropped from the begin- ning of the active line. hcrop1 is not really a zr36067-lv parameter, but it is useful to obtain hstart: hstart = hstart + hcrop1. hcrop2 the number of pixels, that will be dropped from the end of the active line. hcrop2 is not really a zr36067-lv param- eter, but it is useful to obtain hend: hend = hend - hcrop2. vcrop1 the number of lines, that will be dropped from the begin- ning of the active field. vcrop1 is not really a zr36067-lv parameter, but it is useful to obtain vstart: vstart = vstart + vcrop1. vcrop2 the number of lines, that will be dropped from the end of the active field. vcrop2 is not really a zr36067-lv param- eter, but it is useful to obtain vend: vend = vend - vcrop2. hordcm ratio of horizontal decimation. a number of hordcm pixels will be dropped out of every consecutive 64 pixels in an input line. hordcm/64 is the horizontal decimation factor. verdcm ratio of vertical decimation. a number of verdcm pixels will be dropped out of every consecutive 64 lines in an input field. verdcm/64 is the vertical decimation factor. hfilter the horizontal filter through which the input is passed. the filter is selected according to the horizontal decimation factor that is first determined. 49 enhanced pci bus multimedia controller (low-voltage) calculating the horizontal parameters: x and we denote two temporary variables: x = ceil (vidwinwid*64/wa) we = floor (vidwinwid*64/x) hordcm = 64 - x hcrop1 = 2*floor((wa-we)/4) hcrop2 = wa - we - hcrop1 hstart and hend are then calculated from hcrop1 and hcrop2. in the example: x = ceil(597*64/720) = 54 we = floor(597*64/54) = 707 hordcm= 64 - 54 = 10 hcrop1 = 2*floor((720-707)/4) = 6 hcrop2 = 720-707 - 6 = 7 hstart = hstart + hcrop1 = 122 + 6 = 128 hend = hend - hcrop2 = 841 - 7 = 834 (834 - 128 + 1 = 707) the zr36067-lv will actually sample-in 707 pixels from every line. the first 6 and the last 7 active pixels will be cut out. calculating the vertical parameters (regardless of dispmod!) y and he denote two temporary variables: y = ceil (vidwinht*64*2/ha) he = floor (vidwinht*64/y) verdcm = 64 - y vcrop1 = floor((ha/2 - he)/2) vcrop2 = ha/2 - he - vcrop1 vstart and vend are then calculated from vcrop1 and vcrop2. in the example: y = ceil(199*64*2/480) = 54 he = floor(199*64/54) = 235 verdcm= 64 - 54 = 10 vcrop1 = floor(((480/2) - 235) / 2) = 2 vcrop2 = (480/2) - 235 - 2 = 3 vstart = vstart + vcrop1 = 10 + 2 = 12 vend = vend - vcrop2 = 249 - 3 = 246 (246 - 12 + 1 = 235) the zr36067-lv will actually sample-in 235 lines from every field. the first 2 and the last 3 active lines of every field will be cut out. figure 17. input image parameters hsync vsync floor or ceil (ht/s) vstart vend vstart vend hstart hend hstart hend hcrop1 hcrop2 vcrop1 vcrop2 wa ha/2 total size of one input field active portion of one input field the effective portion taken by the zr36120 according to the programmed parameters. (the effective portion can be the entire active field or any partial sub-section of it). ds36067lvr1-0201 the material in this data sheet is for information only. zoran corporation assumes no responsibility for errors or omissions and reserves the right to change, without notice, product specifications, operating characteristics, packaging, etc. zoran corporation assumes no liability for damage resulting from the use of information contained in this document. enhanced pci bus multimedia controller (low-voltage) zr 36067 pq c ordering information screening key pa c k a g e part number prefix pac k ag e screening key c - 0c to +70c (v ddio = 4.75v to 5.25v, v ddc = 3.13v to 3.47v) pq - plastic quad flat pack (eiaj) sales offices trademarks: all brand, product, and company names are trademarks or registered trademarks of their respective companies. u.s. headquarters n zoran corporation 3112 scott blvd. santa clara, ca 95054 usa telephone: 408-919-4111 fax: 408-919-4122 israel design center n zoran microelectronics, ltd. advanced technology center p.o. box 2495 haifa, 31024 israel telephone: +972-4-8545-777 fax: +972-4-8551-550 japan office n zoran japan office 2-2-8 roppongi, minato-ku tokyo 106-0032 japan telephone: +81-3-5574-7081 fax: +81-3-5574-7156 -lv china office n zoran china office suite 2507 electronics science & tech building 2070 central shennan rd. shenzhen, guangdong, 518031 p.r. china telephone: +86-755-378-0319 fax: +86-755-378-0852 taiwan office n zoran taiwan office 4f-1, no. 5, alley 22 lane 513, reikuang rd. taipei, taiwan r.o.c. telephone: +886-2-2659-9797 fax: +886-2-2659-9595 korea office n zoran korea office 505, dongbuk building 45-20, yoido-dong, youngdungpo-ku seoul, korea 150-891 telephone: +82-2-761-7471 fax: +82-2-761-7472 toronto lab n zoran toronto lab 2175 queen st., east, suite 302 toronto, ontario m4e 1e5 canada telephone: 416-690-3356 fax: 416-690-3363 low voltage suffix |
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